External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 817394
Date 7/08/2024
Public
Document Table of Contents

2.3.5. Example: Byte Swizzling for Lockstep Configuration

In lockstep configuration, a DQ lane with a letter s prefix is used as RUSER/WUSER or ECC lane. This lane corresponds to the ECC lane in byte-swizzling notation; it cannot be swapped with other DQS lanes.
Note: Lockstep configuration is supported only on Agilex™ 5 D-Series devices.

DDR4 with sDQ

sDQ[0] maps to the RUSER/WUSER group. It corresponds to the ECC lane in byte-swizzling notation. Because the BYTE_SWIZZLE_CH0 specification can only accept 0,1,2,3,ECC and x, the group number for other DQS groups must be reduced by 1.

This example illustrates the swizzling of DQS group 3 (BL0) with DQS group 2 (BL1), and DQS group 1 (BL2) with DQS group 0 (BL3), respectively.

Table 12.  Lane Placement for x32 + ECC DDR4 Interface
Scheme BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
DDR4/5_AC_TOP DQ[4] DQ[3] DQ[2] DQ[1] AC1 AC2 AC3 sDO[0]
DQS group number in byte swizzling notation 3 2 1 0 X X X ECC
After Byte Swizzle 3 2 0 1 X X X ECC

To achieve this swizzling above, enter the following BYTE_SWIZZLE_CH0 specification in the User Extra Parameters field:

BYTE_SWIZZLE_CH0=2,3,0,1,X,X,X,ECC;

The method to swizzle the DQ pin within a group is the same for lockstep and nonlockstep configuration. Refer to the DQ Pin Swizzling Within DQS group for x32 DDR4 interface example for more information on how to configure DQ Pin Swizzling.