External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4
2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4 x
2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

2.8. Using the Design Example with the Test Engine IP

This topic describes how to use the EMIF design example with the Test Engine IP.

To use your design example with the Test Engine IP, follow these steps:

  1. Change to the following directory:
    <example_design_directory>/qii
  2. At the command line, type the following:
    system-console --script=<path to test engine library.tcl> --sof=<path to sof_file> --update=1 --n-loops=1
    For example:
    system-console --script=hydra_sw/testengine_library.tcl --sof=ed_synth.sof -- update=1 --n-loops=1
    This example reprograms the driver with the traffic pattern in the /bin folder and runs the traffic test for one loop. If you do not want to reprogram the driver, change --update=1 to --update=0.

    When you have enabled all channels, you should see the following output:
    ****  Loop 0  ****
Resetting all drivers ...
Reset complete
Running traffic on all drivers ...
Traffic is now running for all dfrivers
Driver done: 1 / 1
Driver pass: 1 / 1
    For infinite mode, the output does not show that the driver is passing because the traffic continues running. The output is as the follows:
    ****  Loop 0  ****
Resetting all drivers ...
Reset complete
Running ttaffic on all drivers ...
Traffic is now running for all drivers
Driver done: 0 / 1
Unfinished drivers: (0)
Driver pass: 0 / 1
Failed drivers: (0)
    For infinite mode, Altera recommends to monitor the AXI transaction and status_done/status_error of the traffic engine using the Signal Tap Logic Analyzer. Refer to Guidelines for Traffic Generator Status Check in the Debugging chapter of the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs for more information.
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