External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 817394
Date 7/08/2024
Public
Document Table of Contents

2.8. Using the Design Example with the Test Engine IP

This topic describes how to use the EMIF design example with the Test Engine IP.

To use your design example with the Test Engine IP, follow these steps:

  1. Change to the following directory:
    <example_design_directory>/qii
  2. At the command line, type the following:
    system-console --script=<path to test engine library.tcl> --sof=<path to sof_file> --update=1 --n-loops=1
    For example:
    system-console --script=hydra_sw/testengine_library.tcl --sof=ed_synth.sof -- update=1 --n-loops=1
    This example reprograms the driver with the traffic pattern in the /bin folder and runs the traffic test for one loop. If you do not want to reprogram the driver, change --update=1 to --update=0.

    When you have enabled all channels, you should see the following output:
    ****  Loop 0  ****
    Resetting all drivers ...
    Reset complete
    Running traffic on all drivers ...
    Traffic is now running for all dfrivers
    Driver done: 1 / 1
    Driver pass: 1 / 1
    For infinite mode, the output does not show that the driver is passing because the traffic continues running. The output is as the follows:
    ****  Loop 0  ****
    Resetting all drivers ...
    Reset complete
    Running ttaffic on all drivers ...
    Traffic is now running for all drivers
    Driver done: 0 / 1
    Unfinished drivers: (0)
    Driver pass: 0 / 1
    Failed drivers: (0)
    For infinite mode, Altera recommends to monitor the AXI transaction and status_done/status_error of the traffic engine using the Signal Tap Logic Analyzer. Refer to Guidelines for Traffic Generator Status Check in the Debugging chapter of the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs for more information.