External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 817394
Date 7/08/2024
Public
Document Table of Contents

2.3.3. Combining Pin and Byte Swizzling

This example combines the two previous examples, entering the following swizzle parameters:

  • PIN_SWIZZLE_CH0_DQS0=3,1,2,0,4,7,5,6;
  • PIN_SWIZZLE_CH0_DQS2=16,23,18,19,20,21,22,17;
  • BYTE_SWIZZLE_CH0=2,X,X,X,1,0,3,X;

The following table shows the resulting pin placement after DQ pin and byte swizzling.

Table 9.  Lane Placement for Combining Pin and Byte Swizzling Placement
Lane Pin Index Default Effective Pinout
BL5 71 MEM_DQ[23] MEM_DQ[6]
70 MEM_DQ[22] MEM_DQ[5]
69 MEM_DQ[21] MEM_DQ[7]
68 MEM_DQ[20] MEM_DQ[4]
67    
66 MEM_DM_N[2] MEM_DM_N[0]
65 MEM_DQS_C[2] MEM_DQS_C[0]
64 MEM_DQS_T[2] MEM_DQS_T[0]
63 MEM_DQ[19] MEM_DQ[0]
62 MEM_DQ[18] MEM_DQ[2]
61 MEM_DQ[17] MEM_DQ[1]
60 MEM_DQ[16] MEM_DQ[3]
BL0 11 MEM_DQ[7] MEM_DQ[17]
10 MEM_DQ[6] MEM_DQ[22]
9 MEM_DQ[5] MEM_DQ[21]
8 MEM_DQ[4] MEM_DQ[20]
7    
6 MEM_DM_N[0] MEM_DM_N[2]
5 MEM_DQS_C[0] MEM_DQS_C[2]
4 MEM_DQS_T[0] MEM_DQS_T[2]
3 MEM_DQ[3] MEM_DQ[19]
2 MEM_DQ[2] MEM_DQ[18]
1 MEM_DQ[1] MEM_DQ[23]
0 MEM_DQ[0] MEM_DQ[16]