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1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
2.1. Creating an EMIF Project
2.2. Generating and Configuring the EMIF IP
2.3. Configuring DQ Pin Swizzling
2.4. Generating the Synthesizable EMIF Design Example
2.5. Generating the EMIF Design Example for Simulation
2.6. Pin Placement for Agilex™ 5 EMIF IP
2.7. Compiling the Agilex™ 5 EMIF Design Example
2.8. Using the Design Example with the Test Engine IP
2.9. Generating the EMIF Design Example with the Performance Monitor
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface
2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width
2.3.3. Combining Pin and Byte Swizzling
2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface
2.3.5. Example: Byte Swizzling for Lockstep Configuration
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2.3.3. Combining Pin and Byte Swizzling
This example combines the two previous examples, entering the following swizzle parameters:
- PIN_SWIZZLE_CH0_DQS0=3,1,2,0,4,7,5,6;
- PIN_SWIZZLE_CH0_DQS2=16,23,18,19,20,21,22,17;
- BYTE_SWIZZLE_CH0=2,X,X,X,1,0,3,X;
The following table shows the resulting pin placement after DQ pin and byte swizzling.
Lane | Pin Index | Default | Effective Pinout |
---|---|---|---|
BL5 | 71 | MEM_DQ[23] | MEM_DQ[6] |
70 | MEM_DQ[22] | MEM_DQ[5] | |
69 | MEM_DQ[21] | MEM_DQ[7] | |
68 | MEM_DQ[20] | MEM_DQ[4] | |
67 | |||
66 | MEM_DM_N[2] | MEM_DM_N[0] | |
65 | MEM_DQS_C[2] | MEM_DQS_C[0] | |
64 | MEM_DQS_T[2] | MEM_DQS_T[0] | |
63 | MEM_DQ[19] | MEM_DQ[0] | |
62 | MEM_DQ[18] | MEM_DQ[2] | |
61 | MEM_DQ[17] | MEM_DQ[1] | |
60 | MEM_DQ[16] | MEM_DQ[3] | |
BL0 | 11 | MEM_DQ[7] | MEM_DQ[17] |
10 | MEM_DQ[6] | MEM_DQ[22] | |
9 | MEM_DQ[5] | MEM_DQ[21] | |
8 | MEM_DQ[4] | MEM_DQ[20] | |
7 | |||
6 | MEM_DM_N[0] | MEM_DM_N[2] | |
5 | MEM_DQS_C[0] | MEM_DQS_C[2] | |
4 | MEM_DQS_T[0] | MEM_DQS_T[2] | |
3 | MEM_DQ[3] | MEM_DQ[19] | |
2 | MEM_DQ[2] | MEM_DQ[18] | |
1 | MEM_DQ[1] | MEM_DQ[23] | |
0 | MEM_DQ[0] | MEM_DQ[16] |