External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 817394
Date 7/08/2024
Public
Document Table of Contents

3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP

When you parameterize and generate your EMIF IP you can specify that the system create directories for simulation and synthesis file sets, and generate the file sets automatically.

If you set Simulation or Synthesis to True on the Example Design tab, the system creates a complete simulation file set, or a complete synthesis file set, or both, in accordance with your selection.