External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4
2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4 x
2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

2.9. Generating the EMIF Design Example with the Performance Monitor

You can use the Performance Monitor (PMON) to check the performance metrics of the EMIF interface.

The Performance Monitor is a synthesizable block consisting of control and status registers that let you configure and modify the performance metrics of the EMIF Interface. The Performance Monitor allows you to measure the following performance metrics:

  • Read latency
  • Write latency
  • Read efficiency
  • Write efficiency
  • Overall efficiency
  • Subchannel efficiency
  • Subchannel back pressure
  • Expected transactions in subchannel
Figure 32. Enabling the Performance Monitor in the EMIF IP
Note: Do not run any traffic on the interface that PMON is monitoring, while you are configuring PMON. Failure to observe this restriction can result in inaccurate measurements.

To generate a design example with the Performance Monitor, follow these steps:

  1. When generating your design example, set the Enable Performance Monitor parameter to True. This includes the Performance Monitor FPGA IP, which allows you to measure performance on an AIX4 mainband interface.
  2. Open the generated design example and navigate to the Quartus® Prime Pro Edition software folder containing the design example directory:
    <project_directory>/<example_design_directory>/qii/ed_synth.qpf
  3. Make the necessary pin assignments in the .qsf file or by using the Pin Planner and compile the design by clicking Processing > Start Compilation. This generates a .sof file, which you can configure into hardware.
  4. Open the System Console from the Quartus® Prime Pro Edition software by clicking Load Design.
    Figure 33. Load Design
  5. Load the pmon_library.tcl file in the system console by typing the following command:
    source pmon_library.tcl
  6. Load the testengine_library.tcl file in the system console by typing the following command:
    source testengine_library.tcl
  7. Set the metric configuration on desired AXI4 performance monitors:
    • To monitor the read latency only:
      pmon_set_all basic_ro
    • To monitor the write latency only:
      pmon_set_all basic_wo
    • To monitor read and write latency only:
      pmon_set_all basic_rw
    • To monitor read latency, write latency, average number of transactions per cycle:
      pmon_set_all basic_eff
    • For more information on the configurations that you can monitor, use the following command to access to all the metric configurations:
      pmon_help config
  8. Clear the counters and internal state of all performance monitors by typing the following command:
    pmon_reset_counter_data_all
  9. Reset the state of the drivers by typing the following command:
    testengine_reset
  10. Run traffic over the interface by typing the following command:
    testengine_run
  11. Read the efficiency metrics on the AXI4 performance monitor by typing:
    pmon_read_all
    Successful reading of performance metrics produces results similar to that shown below:
    Figure 34. Performance Monitor (PMON) Results
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