External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4
2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4 x
2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4

To generate a custom preset file for LPDDR4, follow these steps:

  1. In the IP Catalog, select Memory Device Description IP (LPDDR4).
    Figure 13. IP Catalog
  2. Type a name for the IP instance and click Create.
    Figure 14. Creating a New IP Instance
  3. Refer to the following figures for the steps in creating and saving the custom presets file:
    Figure 15. Parameterizing EMIF Memory Device Description IP (LPDDR4) – Part 1
    Note:

    Density of Each Memory Die per Channel refers to the density of memory die in each channel. The value remains the same regardless of the number of channels.

    Example:

    If you are using a dual 16-bit channel LPDDR4 component with 4 Gb memory-density-per-channel to implement a 2-channel x 16 LPDDR4 interface, you would set the following parameters in the High-Level Parameters group box:

    Number of Channels = 2

    Density of Each Memory Die per Channel = 4 Gbits

    If you are using a dual 16-bit channel LPDDR4 component with 4 Gb memory-density-per-channel to implement a 1-channel x 32 LPDDR4 interface, you would set the following parameters in the High-Level Parameters group box:

    Number of Channels = 1

    Density of Each Memory Die per Channel = 4 Gbits

    Figure 16. Parameterizing EMIF Memory Device Description IP (LPDDR4) – Part 2

Section Content
Guidelines for Selecting the LPDDR4 Component

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