Visible to Intel only — GUID: rmf1682533074210
Ixiasoft
Visible to Intel only — GUID: rmf1682533074210
Ixiasoft
2.3. Configuring DQ Pin Swizzling
Do not change the location for the EMIF pin using a .qsf assignment or the pin planner if you need to swap the DQ pins within a DQS group or the DQS group to simplify board design. For example, if you implement a x32 DDR4 interface, the EMIF pin location must adhere to the x32 column in the DDR4 Pin Placement table in the Product Architecture chapter of the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs . There is no flexibility to swap the address command pin location.
The following tables summarize the parameters for pin swizzling and byte swizzling, respectively.
Parameter | Description |
---|---|
PIN_SWIZZLE_CH<m>_DQS<n> | Used for swizzling DQ pin within DQS group <n> for channel <m>. m=0 only for DDR4. |
PIN_SWIZZLE_CH<m>_ECC | Used for swizzling DQ pin within the following lane:
|
PIN_SWIZZLE_PRI_DQS<n> | Used for swizzling DQ pin within DQS group <n> in the primary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks. |
PIN_SWIZZLE_SEC_DQS<n> | Used for swizzling DQ pin within DQS group <n> in the secondary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks. |
PIN_SWIZZLE_PRI_ECC | Used for swizzling DQ pin within the ECC lane or RUSER/WUSER lane (when the Extra DQ Byte Lane is enabled), if this lane is implemented in the primary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks. |
PIN_SWIZZLE_SEC_ECC | Used for swizzling DQ pin within the ECC lane or RUSER/WUSER lane (when the Extra DQ Byte Lane is enabled), if this lane is implemented in the secondary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks. |
For device widths of x4 and x8, you can swizzle each DQ pin within its DQS group. For device widths of x16, you can swizzle each DQ pin within the lower byte and upper byte respectively. You cannot swizzle DQ pin for the lower byte to upper byte and vice versa.
Parameter | Description |
---|---|
BYTE_SWIZZLE_CH<m> | Used for swizzling DQS group for CH<m> of the interface. m=0 for DDR4. |
BYTE_SWIZZLE_PRI | Used for swizzling DQS group in the primary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks. |
BYTE_SWIZZLE_SEC | Used for swizzling DQS group in the secondary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks. |
Section Content
Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface
Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width
Combining Pin and Byte Swizzling
Example: Swizzling for x32 + ECC DDR4 Interface
Example: Byte Swizzling for Lockstep Configuration