External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 817394
Date 7/08/2024
Public
Document Table of Contents

2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines

This topic provides high-level guidance for parameterizing the tabs in the Agilex™ 5 EMIF IP parameter editor.
Table 2.  EMIF Parameter Editor Guidelines
Parameter Editor Tab Guidelines
High Level Parameters

Ensure that you correctly enter the following parameters:

  • Technology generation.
  • Memory format.
  • Memory device topology.
  • Memory ranks.
  • Device DQ width (If the device is a DIMM, this specifies the full DQ width of the DIMM. If the interface is composed of discrete components, this specifies the DQ width of each discrete component.)
  • Number of components per rank.
  • ECC Mode.
  • Memory clock frequency.
PHY

Select the desired mode to connect the EMIF IP to user logic:

  • Synchronous fabric.
  • Asynchronous fabric.
Analog Properties Allows you to modify the termination, drive strength, and VREF settings.
Memory Device Preset Selection Refer to the data sheet for your memory device and select the applicable preset.
Controller Configuration Set the controller parameters according to the desired configuration and behavior for your memory controller.
AXI Settings Set the AXI4 data width interface parameters according to your desired configuration.
Additional Parameters Enable you to perform DQ swizzling. Refer to Configuring DQ Pin Swizzling for more information.
Example Design The Example Design tab lets you select which HDL to use for the top-level files, and which file sets you want the design example to generate:
  • Synthesis.
  • Simulation.
  • Core clock frequency.
  • Core reference frequency.
You should make these selections before clicking the Generate Example Design... button. The generated design example is a complete EMIF system consisting of the EMIF IP and a driver to validate the memory interface.
Performance Monitor Enable performance monitor on all channels for measuring read/write transaction metrics.
Traffic Generator Program Allows you to specify the traffic pattern that you want to run:
  • Short mode.
  • Medium mode.
  • Long mode.
  • Infinite mode.
Figure 19. External Memory Interfaces IP Parameter Editor

For detailed information on individual parameters, refer to the appropriate protocol-specific chapter in the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs .