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1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
2.1. Creating an EMIF Project
2.2. Generating and Configuring the EMIF IP
2.3. Configuring DQ Pin Swizzling
2.4. Generating the Synthesizable EMIF Design Example
2.5. Generating the EMIF Design Example for Simulation
2.6. Pin Placement for Agilex™ 5 EMIF IP
2.7. Compiling the Agilex™ 5 EMIF Design Example
2.8. Using the Design Example with the Test Engine IP
2.9. Generating the EMIF Design Example with the Performance Monitor
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface
2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width
2.3.3. Combining Pin and Byte Swizzling
2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface
2.3.5. Example: Byte Swizzling for Lockstep Configuration
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2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines
This topic provides high-level guidance for parameterizing the tabs in the Agilex™ 5 EMIF IP parameter editor.
Parameter Editor Tab | Guidelines |
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High Level Parameters | Ensure that you correctly enter the following parameters:
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PHY | Select the desired mode to connect the EMIF IP to user logic:
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Analog Properties | Allows you to modify the termination, drive strength, and VREF settings. |
Memory Device Preset Selection | Refer to the data sheet for your memory device and select the applicable preset. |
Controller Configuration | Set the controller parameters according to the desired configuration and behavior for your memory controller. |
AXI Settings | Set the AXI4 data width interface parameters according to your desired configuration. |
Additional Parameters | Enable you to perform DQ swizzling. Refer to Configuring DQ Pin Swizzling for more information. |
Example Design | The Example Design tab lets you select which HDL to use for the top-level files, and which file sets you want the design example to generate:
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Performance Monitor | Enable performance monitor on all channels for measuring read/write transaction metrics. |
Traffic Generator Program | Allows you to specify the traffic pattern that you want to run:
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Figure 19. External Memory Interfaces IP Parameter Editor
For detailed information on individual parameters, refer to the appropriate protocol-specific chapter in the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs .