External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 817394
Date 7/08/2024
Public
Document Table of Contents

4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.08 24.2 6.2.0
  • Reorganized some content of the Configuring DQ Pin Swizzling topic into several subtopics.
  • In the Quick Start chapter, modified step 7 in the Generating the EMIF Design Example with the Performance Monitor topic.
2024.04.01 24.1 6.1.0 Initial release.