F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

4.1.1.2. Theory of Operation

The F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP includes a per-port wire named port_state, which signals to the User Logic block that the auto-negotiation (AN) process is complete and the results are ready to be accessed. This signal corresponds to bit[0] of the User_logic_control_in port.
  • Port State Signal:
    • Port_state indicates AN process completion.
    • Corresponds to bit[0] of User_logic_control_in port.
  • When port_state is asserted and AN/LT IP is in PAUSE:
    • The User Logic block asserts relevant resets to the F-Tile Ethernet Multirate Intel® FPGA IP .
    • The User Logic block waits for the corresponding reset acknowledgments.
  • When AN/LT is paused:
    • The User Logic block triggers the appropriate dynamic reconfiguration flow based on the mode selected via a local parameter in the top-level of the example design, passed into the User_logic_control_in port.
    • The F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP and F-Tile Ethernet Multirate Intel® FPGA IP exclusively handle dynamic reconfiguration.
    • The F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP does not perform any dynamic reconfiguration operations.
  • Once dynamic reconfiguration is complete:
    • The User Logic block programs the seq_force_mode register in the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP with the intended data mode rate, if necessary.
    • The User Logic block unpauses the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP
    • The F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP completes the Link Training and moves to data mode.
  • Post-reconfiguration actions:
    • The User Logic block performs the required writes into the F-Tile Ethernet Multirate Intel® FPGA IP soft CSRs.
    • The User Logic block de-asserts resets to the F-Tile Ethernet Multirate Intel® FPGA IP .
In the following Auto-Negotiation and Link Training (AN/LT) + Dynamic Reconfiguration (DR) flow diagram, the blocks enclosed in blue represent the processes executed by the User Logic block.
Figure 23. AN/LT + DR Flow
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