Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.9.4.3.1. Add Post-Fit Nodes when Reusing a Partition Containing a Synthesis Snapshot

You can add post-fit nodes for Signal Tap debug when reusing a design partition containing the synthesis snapshot exported from another project.

To add post-fit nodes to Signal Tap for monitoring:

  1. Open the project that reuses the partition, and then compile the reused partition through the Fitter stage.
  2. Add a Signal Tap instance to the project that reuses the partition, as Step 1: Add the Signal Tap Logic Analyzer to the Project describes.
  3. In the Signal Tap GUI, add the post-fit Signal Tap nodes to the Signal Configuration tab.
  4. Recompile the design from the Place stage by clicking Processing > Start > Start Fitter (Place).
    The Fitter attaches the Signal Tap nodes to the existing synthesized nodes.