External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 10/04/2021
Public

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11.2.3. Transcript Window Messages

When you are debugging a functional issue in simulation, vendor models typically provide much more detailed checks and feedback regarding the interface and their operational requirements than the Intel® generic model.

In general, you should use a vendor-supplied model whenever one is available. Consider using second-source vendor models in preference to the Intel® generic model.

Many issues can be traced to incorrectly configured IP for the specified memory components. Component data sheets usually contain settings information for several different speed grades of memory. Be aware data sheets specify parameters in fixed units of time, frequencies, or clock cycles.

The Intel® generic memory model always matches the parameters specified in the IP, as it is generated using the same engine. Because vendor models are independent of the IP generation process, they offer a more robust IP parameterization check.

During simulation, review the transcript window messages and do not rely on the Simulation Passed message at the end of simulation. This message indicates only that the example driver successfully wrote and then read the correct data for a single test cycle.

Even if the interface functionally passes in simulation, the vendor model may report operational violations in the transcript window. These reported violations often specifically explain why an interface appears to pass in simulation, but fails in hardware.

Vendor models typically perform checks to ensure that the following types of parameters are correct:

  • Burst length
  • Burst order
  • tMRD
  • tMOD
  • tRFC
  • tREFPDEN
  • tRP
  • tRAS
  • tRC
  • tACTPDEN
  • tWR
  • tWRPDEN
  • tRTP
  • tRDPDEN
  • tINIT
  • tXPDLL
  • tCKE
  • tRRD
  • tCCD
  • tWTR
  • tXPR
  • PRECHARGE
  • CAS length
  • Drive strength
  • AL
  • tDQS
  • CAS_WL
  • Refresh
  • Initialization
  • tIH
  • tIS
  • tDH
  • tDS

If a vendor model can verify all these parameters are compatible with your chosen component values and transactions, it provides a specific insight into hardware interface failures.