External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

Download PDF
ID 683216
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP 2. Intel® Agilex™ FPGA EMIF IP – Introduction 3. Intel® Agilex™ FPGA EMIF IP – Product Architecture 4. Intel® Agilex™ FPGA EMIF IP – End-User Signals 5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP 6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support 7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support 8. Intel® Agilex™ FPGA EMIF IP – Timing Closure 9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure 10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization 11. Intel® Agilex™ FPGA EMIF IP – Debugging 12. External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives 13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP x
1.1. Release Information
2. Intel® Agilex™ FPGA EMIF IP – Introduction x
2.1. Intel® Agilex™ EMIF IP Protocol and Feature Support 2.2. Intel® Agilex™ EMIF IP Design Flow 2.3. Intel® Agilex™ EMIF IP Design Checklist
3. Intel® Agilex™ FPGA EMIF IP – Product Architecture x
3.1. Intel® Agilex™ EMIF Architecture: Introduction 3.2. Intel® Agilex™ EMIF Sequencer 3.3. Intel® Agilex™ EMIF Calibration 3.4. Intel® Agilex™ EMIF Controller 3.5. User-requested Reset in Intel® Agilex™ EMIF IP 3.6. Intel® Agilex™ EMIF for Hard Processor Subsystem
3.1. Intel® Agilex™ EMIF Architecture: Introduction x
3.1.1. Intel® Agilex™ EMIF Architecture: I/O Subsystem 3.1.2. Intel® Agilex™ EMIF Architecture: I/O SSM 3.1.3. Intel® Agilex™ EMIF Architecture: I/O Bank 3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane 3.1.5. Intel® Agilex™ EMIF Architecture: Input DQS Clock Tree 3.1.6. Intel® Agilex™ EMIF Architecture: PHY Clock Tree 3.1.7. Intel® Agilex™ EMIF Architecture: PLL Reference Clock Networks 3.1.8. Intel® Agilex™ EMIF Architecture: Clock Phase Alignment
3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane x
3.1.4.1. Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme
3.3. Intel® Agilex™ EMIF Calibration x
3.3.1. Intel® Agilex™ Calibration Stages 3.3.2. Intel® Agilex™ Calibration Stages Descriptions 3.3.3. Intel® Agilex™ Calibration Flowchart 3.3.4. Intel® Agilex™ Calibration Algorithms
3.3.4. Intel® Agilex™ Calibration Algorithms x
3.3.4.1. Calibration Algorithms for DDR4 3.3.4.2. Calibration Algorithms for QDR-IV 3.3.4.3. Guidelines for Debugging Calibration Issues
3.3.4.1. Calibration Algorithms for DDR4 x
3.3.4.1.1. DDR4 Read Calibration 3.3.4.1.2. DDR4 Write Calibration
3.3.4.2. Calibration Algorithms for QDR-IV x
3.3.4.2.1. QDR-IV Read Calibration 3.3.4.2.2. QDR-IV Write Calibration
3.3.4.3. Guidelines for Debugging Calibration Issues x
3.3.4.3.1. Debugging Calibration Failure Using Information from the Calibration report 3.3.4.3.2. Debugging Address and Command Leveling Calibration Failure 3.3.4.3.3. Debugging Address and Command Deskew Failure 3.3.4.3.4. Debugging DQS Enable Failure 3.3.4.3.5. Debugging Read Deskew Calibration Failure 3.3.4.3.6. Debugging VREFIN Calibration Failure 3.3.4.3.7. Debugging LFIFO Calibration Failure 3.3.4.3.8. Debugging Write Leveling Failure 3.3.4.3.9. Debugging Write Deskew Calibration Failure 3.3.4.3.10. Debugging VREFOUT Calibration Failure
3.4. Intel® Agilex™ EMIF Controller x
3.4.1. Hard Memory Controller 3.4.2. Intel® Agilex™ Hard Memory Controller Rate Conversion Feature
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features 3.4.1.2. Hard Memory Controller Main Control Path 3.4.1.3. Data Buffer Controller
3.6. Intel® Agilex™ EMIF for Hard Processor Subsystem x
3.6.1. Restrictions on I/O Bank Usage for Intel® Agilex™ EMIF IP with HPS
4. Intel® Agilex™ FPGA EMIF IP – End-User Signals x
4.1. Intel® Agilex™ EMIF IP Interface and Signal Descriptions 4.2. Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables
4.1. Intel® Agilex™ EMIF IP Interface and Signal Descriptions x
4.1.1. Intel Agilex EMIF IP Interfaces for DDR4 4.1.2. Intel Agilex EMIF IP Interfaces for QDR-IV
4.1.1. Intel Agilex EMIF IP Interfaces for DDR4 x
4.1.1.1. local_reset_req for DDR4 4.1.1.2. local_reset_status for DDR4 4.1.1.3. pll_ref_clk for DDR4 4.1.1.4. pll_locked for DDR4 4.1.1.5. ac_parity_err for DDR4 4.1.1.6. oct for DDR4 4.1.1.7. mem for DDR4 4.1.1.8. status for DDR4 4.1.1.9. afi_reset_n for DDR4 4.1.1.10. afi_clk for DDR4 4.1.1.11. afi_half_clk for DDR4 4.1.1.12. afi for DDR4 4.1.1.13. emif_usr_reset_n for DDR4 4.1.1.14. emif_usr_clk for DDR4 4.1.1.15. ctrl_amm for DDR4 4.1.1.16. ctrl_amm_aux for DDR4 4.1.1.17. ctrl_auto_precharge for DDR4 4.1.1.18. ctrl_user_priority for DDR4 4.1.1.19. ctrl_ecc_user_interrupt for DDR4 4.1.1.20. ctrl_ecc_readdataerror for DDR4 4.1.1.21. ctrl_ecc_status for DDR4 4.1.1.22. ctrl_mmr_slave for DDR4 4.1.1.23. hps_emif for DDR4 4.1.1.24. emif_calbus for DDR4 4.1.1.25. emif_calbus_clk for DDR4
4.1.2. Intel Agilex EMIF IP Interfaces for QDR-IV x
4.1.2.1. local_reset_req for QDR-IV 4.1.2.2. local_reset_status for QDR-IV 4.1.2.3. pll_ref_clk for QDR-IV 4.1.2.4. pll_locked for QDR-IV 4.1.2.5. oct for QDR-IV 4.1.2.6. mem for QDR-IV 4.1.2.7. status for QDR-IV 4.1.2.8. afi_reset_n for QDR-IV 4.1.2.9. afi_clk for QDR-IV 4.1.2.10. afi_half_clk for QDR-IV 4.1.2.11. afi for QDR-IV 4.1.2.12. emif_usr_reset_n for QDR-IV 4.1.2.13. emif_usr_clk for QDR-IV 4.1.2.14. ctrl_amm for QDR-IV 4.1.2.15. emif_calbus for QDR-IV 4.1.2.16. emif_calbus_clk for QDR-IV
4.2. Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables x
4.2.1. ctrlcfg0 4.2.2. ctrlcfg1 4.2.3. dramtiming0 4.2.4. sbcfg1 4.2.5. caltiming0 4.2.6. caltiming1 4.2.7. caltiming2 4.2.8. caltiming3 4.2.9. caltiming4 4.2.10. caltiming9 4.2.11. dramaddrw 4.2.12. sideband0 4.2.13. sideband1 4.2.14. sideband4 4.2.15. sideband6 4.2.16. sideband7 4.2.17. sideband9 4.2.18. sideband11 4.2.19. sideband12 4.2.20. sideband13 4.2.21. sideband14 4.2.22. dramsts 4.2.23. niosreserve0 4.2.24. niosreserve1 4.2.25. sideband16 4.2.26. ecc3: ECC Error and Interrupt Configuration 4.2.27. ecc4: Status and Error Information 4.2.28. ecc5: Address of Most Recent SBE/DBE 4.2.29. ecc6: Address of Most Recent Correction Command Dropped 4.2.30. ecc7: Extension for Address of Most Recent SBE/DBE 4.2.31. ecc8: Extension for Address of Most Recent Correction Command Dropped
5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Options 5.2. Simulation Walkthrough
5.2. Simulation Walkthrough x
5.2.1. Calibration Modes 5.2.2. Simulation Scripts 5.2.3. Functional Simulation with Verilog HDL 5.2.4. Functional Simulation with VHDL 5.2.5. Simulating the Design Example
6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support x
6.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions 6.2. Intel® Agilex™ External Memory Interfaces Intel® Calibration IP Parameters 6.3. Register Map IP-XACT Support for Intel® Agilex™ EMIF DDR4 IP 6.4. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning 6.5. DDR4 Board Design Guidelines
6.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions x
6.1.1. Intel Agilex EMIF IP DDR4 Parameters: General 6.1.2. Intel Agilex EMIF IP DDR4 Parameters: Memory 6.1.3. Intel Agilex EMIF IP DDR4 Parameters: Mem I/O 6.1.4. Intel Agilex EMIF IP DDR4 Parameters: FPGA I/O 6.1.5. Intel Agilex EMIF IP DDR4 Parameters: Mem Timing 6.1.6. Intel Agilex EMIF IP DDR4 Parameters: Controller 6.1.7. Intel Agilex EMIF IP DDR4 Parameters: Diagnostics 6.1.8. Intel Agilex EMIF IP DDR4 Parameters: Example Designs
6.4. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning x
6.4.1. Intel® Agilex™ FPGA EMIF IP Interface Pins 6.4.2. Intel® Agilex™ FPGA EMIF IP Resources 6.4.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP
6.4.1. Intel® Agilex™ FPGA EMIF IP Interface Pins x
6.4.1.1. Estimating Pin Requirements 6.4.1.2. DIMM Options 6.4.1.3. Maximum Number of Interfaces
6.4.2. Intel® Agilex™ FPGA EMIF IP Resources x
6.4.2.1. OCT 6.4.2.2. PLL
6.4.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP x
6.4.3.1. Intel® Agilex™ FPGA EMIF IP Banks 6.4.3.2. General Guidelines 6.4.3.3. x4 DIMM Implementation 6.4.3.4. Specific Pin Connection Requirements 6.4.3.5. Command and Address Signals 6.4.3.6. Clock Signals 6.4.3.7. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.5. DDR4 Board Design Guidelines x
6.5.1. Terminations for DDR4 with Intel® Agilex™ Devices 6.5.2. Clamshell Topology 6.5.3. General Layout Routing Guidelines 6.5.4. Reference Stackup 6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies 6.5.7. Intel® Agilex™ EMIF Pin Swapping Guidelines
6.5.1. Terminations for DDR4 with Intel® Agilex™ Devices x
6.5.1.1. Dynamic On-Chip Termination (OCT) 6.5.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.5.1.3. Choosing Terminations on Intel® Agilex™ FPGA Devices 6.5.1.4. On-Chip Termination Recommendations for Intel® Agilex™ FPGA Devices
6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.5.5.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, LRDIMM, and SODIMM DDR4 Topologies 6.5.5.2. Two DIMMs per Channel (2DPC) for UDIMM, RDIMM, and LRDIMM DDR4 Topologies 6.5.5.3. Two DIMMs per Channel (2DPC) for SODIMM Topology 6.5.5.4. Skew Matching Guidelines for DIMM Configurations 6.5.5.5. Power Delivery Recommendations for the Memory / DIMM Side
6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.5.6.1. Single Rank x 8 Discrete (Component) Topology 6.5.6.2. Single Rank x 16 Discrete (Component) Topology 6.5.6.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and R Rank x 16 Discrete (Component) Topologies 6.5.6.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.5.6.5. Power Delivery Recommendations for DDR4 Discrete Configurations
7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support x
7.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions 7.2. Intel® Agilex™ External Memory Interfaces Intel® Calibration IP Parameters 7.3. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning 7.4. QDR-IV Board Design Guidelines
7.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions x
7.1.1. Intel Agilex EMIF IP QDR-IV Parameters: General 7.1.2. Intel Agilex EMIF IP QDR-IV Parameters: Memory 7.1.3. Intel Agilex EMIF IP QDR-IV Parameters: FPGA I/O 7.1.4. Intel Agilex EMIF IP QDR-IV Parameters: Mem Timing 7.1.5. Intel Agilex EMIF IP QDR-IV Parameters: Controller 7.1.6. Intel Agilex EMIF IP QDR-IV Parameters: Diagnostics 7.1.7. Intel Agilex EMIF IP QDR-IV Parameters: Example Designs
7.3. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning x
7.3.1. Intel® Agilex™ FPGA EMIF IP Interface Pins 7.3.2. Intel® Agilex™ FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP
7.3.1. Intel® Agilex™ FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. Maximum Number of Interfaces
7.3.2. Intel® Agilex™ FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP x
7.3.3.1. Intel® Agilex™ FPGA EMIF IP Banks 7.3.3.2. General Guidelines 7.3.3.3. QDR IV SRAM Commands and Addresses, AP, and AINV Signals 7.3.3.4. QDR IV SRAM Clock Signals 7.3.3.5. QDR IV SRAM Data, DINV, and QVLD Signals 7.3.3.6. Specific Pin Connection Requirements 7.3.3.7. Resource Sharing Guidelines (Multiple Interfaces)
7.4. QDR-IV Board Design Guidelines x
7.4.1. General Layout Routing Guidelines 7.4.2. Reference Stackup 7.4.3. Routing Guidelines for QDR-IV Topology 7.4.4. Intel® Agilex™ EMIF Design Guideline Summary
7.4.3. Routing Guidelines for QDR-IV Topology x
7.4.3.1. QDR-IV Single Device Memory Topology 7.4.3.2. Skew Matching Guidelines for QDR-IV Configurations 7.4.3.3. Power Delivery Recommendation for QDR-IV Configurations
8. Intel® Agilex™ FPGA EMIF IP – Timing Closure x
8.1. Timing Closure 8.2. Optimizing Timing
8.1. Timing Closure x
8.1.1. Timing Analysis
8.1.1. Timing Analysis x
8.1.1.1. PHY or Core
9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure x
9.1. I/O Timing Closure Overview 9.2. Collateral Generated with Your EMIF IP 9.3. SPICE Decks 9.4. File Organization 9.5. Top-level Parameterization File 9.6. IP-Supplied Parameters that You Might Need to Override 9.7. Multi-Rank Topology 9.8. Pin Parasitics 9.9. Mask Evaluation
9.3. SPICE Decks x
9.3.1. Address/Command Simulation Deck 9.3.2. FPGA Write Operation Simulation Deck 9.3.3. FPGA Read Operation Simulation Deck
10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Auto-Precharge Commands 10.4.2. Additive Latency 10.4.3. Bank Interleaving 10.4.4. Additive Latency and Bank Interleaving 10.4.5. User-Controlled Refresh 10.4.6. Frequency of Operation 10.4.7. Series of Reads or Writes 10.4.8. Data Reordering 10.4.9. Starvation Control 10.4.10. Command Reordering 10.4.11. Bandwidth 10.4.12. Enable Command Priority Control 10.4.13. Controller Pre-pay and Post-pay Refresh (DDR4 Only)
10.4.1. Auto-Precharge Commands x
10.4.1.1. Using Auto-precharge to Achieve Highest Memory Bandwidth for DDR4 Interfaces
11. Intel® Agilex™ FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Hardware Debugging Guidelines 11.6. Categorizing Hardware Issues 11.7. Debugging with the External Memory Interface Debug Toolkit 11.8. Using the Default Traffic Generator 11.9. Using the Configurable Traffic Generator (TG2) 11.10. EMIF On-Chip Debug Port 11.11. Efficiency Monitor
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages 11.2.4. Modifying the Example Driver to Replicate the Failure
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer x
11.4.1. Signals to Monitor with the Signal Tap Logic Analyzer
11.5. Hardware Debugging Guidelines x
11.5.1. Create a Simplified Design that Demonstrates the Same Issue 11.5.2. Measure Power Distribution Network 11.5.3. Measure Signal Integrity and Setup and Hold Margin 11.5.4. Vary Voltage 11.5.5. Operate at a Lower Speed 11.5.6. Determine Whether the Issue Exists in Previous Versions of Software 11.5.7. Determine Whether the Issue Exists in the Current Version of Software 11.5.8. Try A Different PCB 11.5.9. Try Other Configurations 11.5.10. Debugging Checklist
11.6. Categorizing Hardware Issues x
11.6.1. Signal Integrity Issues 11.6.2. Hardware and Calibration Issues
11.6.1. Signal Integrity Issues x
11.6.1.1. Characteristics of Signal Integrity Issues 11.6.1.2. Evaluating Signal Integrity Issues
11.6.1.2. Evaluating Signal Integrity Issues x
11.6.1.2.1. Skew 11.6.1.2.2. Crosstalk 11.6.1.2.3. Power System 11.6.1.2.4. Clock Signals 11.6.1.2.5. Address and Command Signals 11.6.1.2.6. Read Data Valid Window and Eye Diagram 11.6.1.2.7. Write Data Valid Window and Eye Diagram 11.6.1.2.8. OCT and ODT Usage
11.6.2. Hardware and Calibration Issues x
11.6.2.1. Postamble Timing Issues and Margin 11.6.2.2. Intermittent Issue Evaluation
11.7. Debugging with the External Memory Interface Debug Toolkit x
11.7.1. Prerequisites for Using the EMIF Debug Toolkit 11.7.2. Configuring a Design to Use the Toolkit 11.7.3. Launching the EMIF Debug Toolkit 11.7.4. Using the EMIF Debug Toolkit 11.7.5. Exporting Tables 11.7.6. Viewing Reports Graphically in the Eye Viewer
11.7.2. Configuring a Design to Use the Toolkit x
11.7.2.1. Generating a Design Example with the Debug Toolkit 11.7.2.2. Creating a Design Example with Multiple External Memory Interfaces 11.7.2.3. Enabling the EMIF Toolkit in an Existing Design
11.7.4. Using the EMIF Debug Toolkit x
11.7.4.1. Memory Configuration Tab 11.7.4.2. Calibration Tab 11.7.4.3. Guidelines for Debugging Calibration Issues 11.7.4.4. Calibration Report Tab 11.7.4.5. Calibrate Termination Tab 11.7.4.6. Vref Margining Tab 11.7.4.7. Driver Margining Tab 11.7.4.8. ISSPs Tab 11.7.4.9. Pin Delay Settings Tab
11.7.4.2. Calibration Tab x
11.7.4.2.1. Rerunning Calibration 11.7.4.2.2. Rerunning the Traffic Generator
11.7.4.3. Guidelines for Debugging Calibration Issues x
11.7.4.3.1. Debugging Calibration Failure Using Information from the Calibration report 11.7.4.3.2. Debugging Address and Command Leveling Calibration Failure 11.7.4.3.3. Debugging Address and Command Deskew Failure 11.7.4.3.4. Debugging DQS Enable Failure 11.7.4.3.5. Debugging Read Deskew Calibration Failure 11.7.4.3.6. Debugging VREFIN Calibration Failure 11.7.4.3.7. Debugging LFIFO Calibration Failure 11.7.4.3.8. Debugging Write Leveling Failure 11.7.4.3.9. Debugging Write Deskew Calibration Failure 11.7.4.3.10. Debugging VREFOUT Calibration Failure
11.8. Using the Default Traffic Generator x
11.8.1. Reading the Default Traffic Generator Status 11.8.2. Running Infinite Traffic using the Default Traffic Generator 11.8.3. Changing the Reset Trigger of the Default Traffic Generator 11.8.4. Observing Generated Traffic with Signal Tap
11.9. Using the Configurable Traffic Generator (TG2) x
11.9.1. Enabling the Traffic Generator in a Design Example 11.9.2. Traffic Generator Block Description 11.9.3. Default Traffic Pattern 11.9.4. Configuration and Status Registers 11.9.5. User Pattern 11.9.6. Traffic Generator Status 11.9.7. Starting Traffic with the Traffic Generator 11.9.8. Traffic Generator Configuration User Interface
11.9.5. User Pattern x
11.9.5.1. Test Duration / Instruction pattern 11.9.5.2. Address Pattern 11.9.5.3. Data Pattern and Byte Enable
11.9.5.2. Address Pattern x
11.9.5.2.1. Address Generator Modes 11.9.5.2.2. Address Generator MSB Indices 11.9.5.2.3. Address Generator Effective Width 11.9.5.2.4. Address Generator Relative Frequencies 11.9.5.2.5. Address Pattern Examples - Basic Mode 11.9.5.2.6. Address Pattern Examples - Advanced Mode
11.9.8. Traffic Generator Configuration User Interface x
11.9.8.1. Connecting the Traffic Generator 11.9.8.2. Configuring the Traffic Generator 11.9.8.3. Traffic Generator Preset Selection 11.9.8.4. Traffic Generator Status Report 11.9.8.5. Examples of Configuring the TG2 Traffic Generator
11.10. EMIF On-Chip Debug Port x
11.10.1. Enabling the On-Chip Debug Port 11.10.2. I/O SSM calbus Bridge Data Structures and Usage 11.10.3. I/O SSM User-RAM Data Structures and Usage 11.10.4. Debug Interface Structure 11.10.5. Example: Reading Calibration Results and Margins with the On-Chip Debug Port
11.10.3. I/O SSM User-RAM Data Structures and Usage x
11.10.3.1. Parameter Tables 11.10.3.2. Parameter Table Enums
11.10.3.1. Parameter Tables x
11.10.3.1.1. Global Parameter Table 11.10.3.1.2. Per-interface Parameter Table Structure 11.10.3.1.3. Parameter Table Arrays
11.10.4. Debug Interface Structure x
11.10.4.1. Debug Data Structures debug_data_struct (pt_DEBUG_DATA_PTR) mem_summary_report (mem_summary_report_pointer) mem_cal_report (mem_cal_report_pointer) debug_cal_data_struct 11.10.4.2. Debug Enums
11.11. Efficiency Monitor x
11.11.1. Enabling the Efficiency Monitor in a Design Example 11.11.2. Efficiency Monitor Block Descriptions 11.11.3. Control and Status Registers 11.11.4. Opening the Efficiency Monitor Toolkit
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP
2. Intel® Agilex™ FPGA EMIF IP – Introduction
3. Intel® Agilex™ FPGA EMIF IP – Product Architecture
4. Intel® Agilex™ FPGA EMIF IP – End-User Signals
5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP
6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support
7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support
8. Intel® Agilex™ FPGA EMIF IP – Timing Closure
9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure
10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization
11. Intel® Agilex™ FPGA EMIF IP – Debugging
12. External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives
13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

11.10.4.1. Debug Data Structures

This topic describes how to navigate the debug structures in the user-RAM.

debug_data_struct (pt_DEBUG_DATA_PTR)

The debug_data_struct’s base address is equal to: (user_ram base address) + (offset for debug_data_struct, read from pt_DEBUG_DATA_PTR)

If you have enabled debug in this row, this structure is populated and the pointer (pt_DEBUG_DATA_PTR) is stored in the parameter table after calibration. This structure provides the following:
  1. An interface by which to view the state of calibration, by checking the status bit in the debug_data_struct:
    • Bit 1 is set if calibration has started.
    • Bit 2 is set if calibration has finished.
  2. An interface by which to send commands to the firmware (available commands are described by ENUM_INTERFACE_COMMANDS) and receive response codes about the command status (recognized status codes are described by ENUM_DEBUG_INTERFACE_COMMAND_STATUS_CODES). Sending a command should follow this procedure:
    1. Wait for command_status to be TX_STATUS_CMD_READY.
    2. Set any relevant command_parameters for the desired command (described in ENUM_INTERFACE_COMMANDS).
    3. Set the requested_command code (ENUM_INTERFACE_COMMANDS).
    4. Wait for command_status to be TX_STATUS_RESPONSE_READY.
    5. Set requested_command code to CMD_RESPONSE_ACK to acknowledge the response was received.
    6. Any following command can be send once command_status returns to the value TX_STATUS_CMD_READY.
  3. A pointer to mem_summary_report, which provides a more detailed status of calibration.
  4. A pointer to mem_cal_report, which provides details of settings that were decided during calibration (such as delay settings, margins, vref settings, and so forth).

Example 1: Steps to Request Full EMIF Recalibration

  1. Read from command_status. Wait until the readdata=32’h0000_0000 (TX_STATUS_CMD_READY)
  2. Write to command_parameters[0] with writedata=Interface_ID that you want to calibrate. (If you have only one interface, set the writedata=32’h0000_0000.)
  3. Write to command_parameters[1] with writedata=32’h0000_0003(DYNAMIC_FULL_RECAL). (Refer to ENUM_INIT_MODE table for other supported calibration options.)
  4. Write to requested_command with writedata=32’h0000_0005(RUN_MEM_CALIBRATE).
  5. Read from command_status. Wait until the readdata=32’h0000_0003 (TX_STATUS_RESPONSE_READY).
  6. Write to requested_command with writedata=32’h0000_0001(CMD_RESPONSE_ACK).

Example 2: Set the Starting value of VREF_OUT and Recalibrate EMIF using New Starting Value

  1. Read from command_status. Wait till the readdata=32’h0000_0000 (TX_STATUS_CMD_READY).
  2. Set the new VREF_OUT. Refer to debug_cal_data_struct for information on how to determine the Vref_setting and Vref_range.
    1. Write to command_parameters[0] with writedata=Vref_setting.
    2. Write to command_parameters[1] with writedata=Vref_range.
    3. Write to requested_command with writedata=32’h0000_001B(SET_VREF_OUT).
    4. Read from command_status. Wait till the readdata=32’h0000_0003 (TX_STATUS_RESPONSE_READY).
    5. Write to requested_command with writedata=32’h0000_0001(CMD_RESPONSE_ACK).
  3. Request Recalibration. Follow steps in Example 1 but set init_mode to SKIP_INIT_VREF.

Example 3: Hardcode the VREF_IN and VREF_OUT and bypass the VREFCAL in next EMIF Recalibration

  1. Set the new VREF_OUT. Refer to debug_cal_data_struct for information on how to determine the Vref_setting and Vref_range.
    1. Read from command_status. Wait till the readdata=32’h0000_0000 (TX_STATUS_CMD_READY).
    2. Write to command_parameters[0] with writedata=Vref_setting.
    3. Write to command_parameters[1] with writedata=Vref_range.
    4. Write to requested_command with writedata=32’h0000_001B(SET_VREF_OUT).
    5. Read from command_status. Wait till the readdata=32’h0000_0003 (TX_STATUS_RESPONSE_READY).
    6. Write to requested_command with writedata=32’h0000_0001(CMD_RESPONSE_ACK).
  2. Set the new VREF_IN. Refer to debug_cal_data_struct for information on how to determine the Vref_setting and Vref_range.
    1. Read from command_status. Wait till the readdata=32’h0000_0000 (TX_STATUS_CMD_READY).
    2. Write to command_parameters[0] with writedata=Vref_setting.
    3. Write to requested_command with writedata=32’h0000_001A(SET_VREF_IN).
    4. Read from command_status. Wait till the readdata=32’h0000_0003 (TX_STATUS_RESPONSE_READY).
    5. Write to requested_command with writedata=32’h0000_0001(CMD_RESPONSE_ACK).
  3. Set the calibration to skip VREF_IN can VREF_OUT.
    1. Read from command_status. Wait till the readdata=32’h0000_0000 (TX_STATUS_CMD_READY).
    2. Write to command_parameters[0] with writedata=32'h 0000 C000 (CALIB_SKIP_VREFIN_CAL | CALIB_SKIP_VREFOUT_CAL).
    3. Write to requested_command with writedata= 32'h 0000 001E (SET_SKIP_STEPS).
    4. Read from command_status. Wait till the readdata=32’h0000_0003 (TX_STATUS_RESPONSE_READY).
  4. Start EMIF calibration. Follow the same steps as in example 1, but set init_mode to SKIP_INIT_VREF.

Parameter Offset Within Structure Size Purpose
data_size 0 32 size of this structure (in bytes).
status 4 32 output: calibration status (ENUM_CAL_ERROR).
requested_command 8 32 input: a command that the user wishes for firmware to perform (ENUM_INTERFACE_COMMANDS).
command_status 12 32 output: status of the command that a user requested (ENUM_DEBUG_INTERFACE_COMMAND_STATUS_CODES).
command_parameters[0] 16 32 input: a parameter for a requested_command. The relevant parameters for each command are described in ENUM_DEBUG_INTERFACE_COMMANDS.
command_parameters[1] 20 32 input: a parameter for a requested_command. The relevant parameters for each command are described in ENUM_DEBUG_INTERFACE_COMMANDS.
command_parameters[2] 24 32 input: a parameter for a requested_command. The relevant parameters for each command are described in ENUM_DEBUG_INTERFACE_COMMANDS.
command_parameters[3] 28 32 input: a parameter for a requested_command. The relevant parameters for each command are described in ENUM_DEBUG_INTERFACE_COMMANDS.
mem_summary_report_pointer 32 32 output: pointer to the mem_summary_report structure.
mem_cal_report_pointer 36 32 output: pointer to the mem_cal_report structure.

mem_summary_report (mem_summary_report_pointer)

This structure provides details about the status of calibration.

Parameter Offset Within Structure Size Comments
data_size 0 32 The size of this structure (in bytes).
report_flags 4 32

bit[0]: is 1 if report is ready, and all the registers below are valid.

bits[23:1]: reserved for future use.

bits[31:24]: version number of this report.
error_stage 12 32 The first stage at which calibration has failed (ENUM_CAL_STAGE).
error_group 16 32 Each bit corresponds to a dqs group. If a bit is set 1, then the corresponding group failed in the stage indicated by error_stage.
error_code 20 32 Detailed calibration status (ENUM_CAL_ERROR).
in_out_rate 72 8

bits [7:4] = out_rate = vco : mem_clk.

bits [3:0] = in_rate = mem_clk : phy_clk ratio.

cur_interface_idx 32 32 ID of the interface to which the stored debug information applies — that is, the latest interface to have been calibrated.

mem_cal_report (mem_cal_report_pointer)

This structure provides details of settings observed during calibration (such as delay settings, margins, vref settings, etc).

Parameter Offset Within Structure Number of Elements in Array (1 if not an array) Size of Each Element in Array
data_size 0 1 32
debug_cal_data_struct_pointer__cal_data_dq_in 4 num_dq 32
debug_cal_data_struct_pointer__cal_data_dq_out 8 num_dq 32
debug_cal_data_struct_pointer__cal_data_dm_dbi_in 12 num_dm 32
debug_cal_data_struct_pointer__cal_data_dm_dbi_out 16 num_dm 32
debug_cal_data_struct_pointer__cal_data_dqs_in 20 num_dqs_rd 32
debug_cal_data_struct_pointer__cal_data_dqs_en 24 num_dqs_rd 32
debug_cal_data_struct_pointer__cal_data_dqs_en_b 28 num_dqs_rd 32
debug_cal_data_struct_pointer__cal_data_dqs_out 32 num_dqs_wr 32
debug_cal_data_struct_pointer__vrefin 36 num_dqs_rd 32
debug_cal_data_struct_pointer__vrefout 40 num_dqs_wr 32
debug_cal_data_struct_pointer__cal_data_ca 44 num_ac_rom_enums 32
debug_cal_data_struct_pointer__vfifo 52 num_dqs_rd 8
debug_cal_data_struct_pointer__lfifo 56 num_dqs_rd 8
debug_cal_data_struct_pointer__dcc_dq_in 60 num_dq 8
debug_cal_data_struct_pointer__dcc_dq_out 64 num_dq 8
debug_cal_data_struct_pointer__dcc_dm_dbi_in 68 num_dm 8
debug_cal_data_struct_pointer__dcc_dm_dbi_out 72 num_dm 8
debug_cal_data_struct_pointer__dcc_dqs_in 76 num_dqs_rd 8
debug_cal_data_struct_pointer__dcc_dqs_out 80 num_dqs_wr 8
debug_cal_data_struct_pointer__dcc_ca 84 num_ac_rom_enums 8
debug_cal_data_struct_pointer__vrefout_all_ranks 88 num_dqs_wr 8
debug_cal_data_struct_pointer__ctle_out 92 num_dqs_wr 8
debug_cal_data_struct_pointer__ctle_in_dq 96 num_dq 8
debug_cal_data_struct_pointer__ctle_in_dqs 100 num_dqs_rd 8
write_lat 108 1 32
read_lat 112 1 32
rank_skew_data_out 116 1 32
rank_skew_dqsen 120 1 32
extra_rank_delay_any_to_read 124 1 32
extra_rank_delay_any_to_write 128 1 32

debug_cal_data_struct

This data structure is instantiated many times and is pointed to by each debug_cal_data_struct_pointer__* in the mem_cal_report. The setting field stores the chosen setting for the given parameter, while the left_edge and right_edge fields store the offset from the setting, for which transactions were found to still pass. To interpret the values stored, observe the following:

  • For a timing parameter, all three fields are stored in taps.
  • For a voltage parameter, the setting field is as follows:
    • Bits[15:8] = vref_range. This is set during IP parameterization.
      • Value 0 has a range of 60-92.5% of the VCCIO/VREFDQ.
      • Value 1 has range of 45-77.5% of the VCCIO/VREFDQ.
    • Bits[7:0] = vref_setting decided during calibration, as the number of incremental steps within the range (where each step is 0.65%).

      For example, in DDR4, the VCCIO voltage is 1.2V. So, given the setting = 0x0122:

      Vref_range=1, vref_setting=34

      Therefore, to calculate the Vref value in volts: ((34 × 0.0065) + 0.45) × 1.2V) = 0.805V

Parameter Offset Within Structure Size
setting 0 16
left_edge 2 8
right_edge 3 8
Level Two Title