External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 10/04/2021
Public

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6.5.6.4. Skew Matching Guidelines for DDR4 Discrete Configurations

This topic describes skew matching guidelines for single rank x 8 and single rank x 16 topologies.

Observe the following rules when skew matching DDR4 discrete configurations:

  • Perform skew matching in time (picoseconds) rather than in actual trace length, to better account for via delays when signals are routed on different layers.
  • Include both package per-pin skew and PCB delay when performing skew matching.
  • Skew (length) matching for the alert signal is not required.

The following table provides skew matching guidelines for DDR4 down-memory topologies.

Table 109.  DDR4 Skew Matching Guidelines
DDR4 Device-down Length Matching Rules Length Matching in Time (ps)
Skew matching between DQS and CLK -85ps < CLK - DQS < 935ps
Skew matching between DQ and DQS within byte -3.5ps < DQ - DQS < 3.5ps
Skew matching between DQS and DQS# < 1ps
Skew matching between CLK and CLK# < 1ps
Skew matching between CMD/ADDR/CTRL and Clock -20ps < CLK - CMD/ADDR/CTRL < 20ps
Skew matching among CMD/ADDR/CTRL within each channel < 20ps
Include package length in skew matching for FPGA device with no migration Required
Include package length in skew matching for FPGA device with migration Not Recommended