External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

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ID 683216
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP 2. Intel® Agilex™ FPGA EMIF IP – Introduction 3. Intel® Agilex™ FPGA EMIF IP – Product Architecture 4. Intel® Agilex™ FPGA EMIF IP – End-User Signals 5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP 6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support 7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support 8. Intel® Agilex™ FPGA EMIF IP – Timing Closure 9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure 10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization 11. Intel® Agilex™ FPGA EMIF IP – Debugging 12. External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives 13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP x
1.1. Release Information
2. Intel® Agilex™ FPGA EMIF IP – Introduction x
2.1. Intel® Agilex™ EMIF IP Protocol and Feature Support 2.2. Intel® Agilex™ EMIF IP Design Flow 2.3. Intel® Agilex™ EMIF IP Design Checklist
3. Intel® Agilex™ FPGA EMIF IP – Product Architecture x
3.1. Intel® Agilex™ EMIF Architecture: Introduction 3.2. Intel® Agilex™ EMIF Sequencer 3.3. Intel® Agilex™ EMIF Calibration 3.4. Intel® Agilex™ EMIF Controller 3.5. User-requested Reset in Intel® Agilex™ EMIF IP 3.6. Intel® Agilex™ EMIF for Hard Processor Subsystem
3.1. Intel® Agilex™ EMIF Architecture: Introduction x
3.1.1. Intel® Agilex™ EMIF Architecture: I/O Subsystem 3.1.2. Intel® Agilex™ EMIF Architecture: I/O SSM 3.1.3. Intel® Agilex™ EMIF Architecture: I/O Bank 3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane 3.1.5. Intel® Agilex™ EMIF Architecture: Input DQS Clock Tree 3.1.6. Intel® Agilex™ EMIF Architecture: PHY Clock Tree 3.1.7. Intel® Agilex™ EMIF Architecture: PLL Reference Clock Networks 3.1.8. Intel® Agilex™ EMIF Architecture: Clock Phase Alignment
3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane x
3.1.4.1. Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme
3.3. Intel® Agilex™ EMIF Calibration x
3.3.1. Intel® Agilex™ Calibration Stages 3.3.2. Intel® Agilex™ Calibration Stages Descriptions 3.3.3. Intel® Agilex™ Calibration Flowchart 3.3.4. Intel® Agilex™ Calibration Algorithms
3.3.4. Intel® Agilex™ Calibration Algorithms x
3.3.4.1. Calibration Algorithms for DDR4 3.3.4.2. Calibration Algorithms for QDR-IV 3.3.4.3. Guidelines for Debugging Calibration Issues
3.3.4.1. Calibration Algorithms for DDR4 x
3.3.4.1.1. DDR4 Read Calibration 3.3.4.1.2. DDR4 Write Calibration
3.3.4.2. Calibration Algorithms for QDR-IV x
3.3.4.2.1. QDR-IV Read Calibration 3.3.4.2.2. QDR-IV Write Calibration
3.3.4.3. Guidelines for Debugging Calibration Issues x
3.3.4.3.1. Debugging Calibration Failure Using Information from the Calibration report 3.3.4.3.2. Debugging Address and Command Leveling Calibration Failure 3.3.4.3.3. Debugging Address and Command Deskew Failure 3.3.4.3.4. Debugging DQS Enable Failure 3.3.4.3.5. Debugging Read Deskew Calibration Failure 3.3.4.3.6. Debugging VREFIN Calibration Failure 3.3.4.3.7. Debugging LFIFO Calibration Failure 3.3.4.3.8. Debugging Write Leveling Failure 3.3.4.3.9. Debugging Write Deskew Calibration Failure 3.3.4.3.10. Debugging VREFOUT Calibration Failure
3.4. Intel® Agilex™ EMIF Controller x
3.4.1. Hard Memory Controller 3.4.2. Intel® Agilex™ Hard Memory Controller Rate Conversion Feature
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features 3.4.1.2. Hard Memory Controller Main Control Path 3.4.1.3. Data Buffer Controller
3.6. Intel® Agilex™ EMIF for Hard Processor Subsystem x
3.6.1. Restrictions on I/O Bank Usage for Intel® Agilex™ EMIF IP with HPS
4. Intel® Agilex™ FPGA EMIF IP – End-User Signals x
4.1. Intel® Agilex™ EMIF IP Interface and Signal Descriptions 4.2. Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables
4.1. Intel® Agilex™ EMIF IP Interface and Signal Descriptions x
4.1.1. Intel Agilex EMIF IP Interfaces for DDR4 4.1.2. Intel Agilex EMIF IP Interfaces for QDR-IV
4.1.1. Intel Agilex EMIF IP Interfaces for DDR4 x
4.1.1.1. local_reset_req for DDR4 4.1.1.2. local_reset_status for DDR4 4.1.1.3. pll_ref_clk for DDR4 4.1.1.4. pll_locked for DDR4 4.1.1.5. ac_parity_err for DDR4 4.1.1.6. oct for DDR4 4.1.1.7. mem for DDR4 4.1.1.8. status for DDR4 4.1.1.9. afi_reset_n for DDR4 4.1.1.10. afi_clk for DDR4 4.1.1.11. afi_half_clk for DDR4 4.1.1.12. afi for DDR4 4.1.1.13. emif_usr_reset_n for DDR4 4.1.1.14. emif_usr_clk for DDR4 4.1.1.15. ctrl_amm for DDR4 4.1.1.16. ctrl_amm_aux for DDR4 4.1.1.17. ctrl_auto_precharge for DDR4 4.1.1.18. ctrl_user_priority for DDR4 4.1.1.19. ctrl_ecc_user_interrupt for DDR4 4.1.1.20. ctrl_ecc_readdataerror for DDR4 4.1.1.21. ctrl_ecc_status for DDR4 4.1.1.22. ctrl_mmr_slave for DDR4 4.1.1.23. hps_emif for DDR4 4.1.1.24. emif_calbus for DDR4 4.1.1.25. emif_calbus_clk for DDR4
4.1.2. Intel Agilex EMIF IP Interfaces for QDR-IV x
4.1.2.1. local_reset_req for QDR-IV 4.1.2.2. local_reset_status for QDR-IV 4.1.2.3. pll_ref_clk for QDR-IV 4.1.2.4. pll_locked for QDR-IV 4.1.2.5. oct for QDR-IV 4.1.2.6. mem for QDR-IV 4.1.2.7. status for QDR-IV 4.1.2.8. afi_reset_n for QDR-IV 4.1.2.9. afi_clk for QDR-IV 4.1.2.10. afi_half_clk for QDR-IV 4.1.2.11. afi for QDR-IV 4.1.2.12. emif_usr_reset_n for QDR-IV 4.1.2.13. emif_usr_clk for QDR-IV 4.1.2.14. ctrl_amm for QDR-IV 4.1.2.15. emif_calbus for QDR-IV 4.1.2.16. emif_calbus_clk for QDR-IV
4.2. Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables x
4.2.1. ctrlcfg0 4.2.2. ctrlcfg1 4.2.3. dramtiming0 4.2.4. sbcfg1 4.2.5. caltiming0 4.2.6. caltiming1 4.2.7. caltiming2 4.2.8. caltiming3 4.2.9. caltiming4 4.2.10. caltiming9 4.2.11. dramaddrw 4.2.12. sideband0 4.2.13. sideband1 4.2.14. sideband4 4.2.15. sideband6 4.2.16. sideband7 4.2.17. sideband9 4.2.18. sideband11 4.2.19. sideband12 4.2.20. sideband13 4.2.21. sideband14 4.2.22. dramsts 4.2.23. niosreserve0 4.2.24. niosreserve1 4.2.25. sideband16 4.2.26. ecc3: ECC Error and Interrupt Configuration 4.2.27. ecc4: Status and Error Information 4.2.28. ecc5: Address of Most Recent SBE/DBE 4.2.29. ecc6: Address of Most Recent Correction Command Dropped 4.2.30. ecc7: Extension for Address of Most Recent SBE/DBE 4.2.31. ecc8: Extension for Address of Most Recent Correction Command Dropped
5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Options 5.2. Simulation Walkthrough
5.2. Simulation Walkthrough x
5.2.1. Calibration Modes 5.2.2. Simulation Scripts 5.2.3. Functional Simulation with Verilog HDL 5.2.4. Functional Simulation with VHDL 5.2.5. Simulating the Design Example
6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support x
6.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions 6.2. Intel® Agilex™ External Memory Interfaces Intel® Calibration IP Parameters 6.3. Register Map IP-XACT Support for Intel® Agilex™ EMIF DDR4 IP 6.4. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning 6.5. DDR4 Board Design Guidelines
6.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions x
6.1.1. Intel Agilex EMIF IP DDR4 Parameters: General 6.1.2. Intel Agilex EMIF IP DDR4 Parameters: Memory 6.1.3. Intel Agilex EMIF IP DDR4 Parameters: Mem I/O 6.1.4. Intel Agilex EMIF IP DDR4 Parameters: FPGA I/O 6.1.5. Intel Agilex EMIF IP DDR4 Parameters: Mem Timing 6.1.6. Intel Agilex EMIF IP DDR4 Parameters: Controller 6.1.7. Intel Agilex EMIF IP DDR4 Parameters: Diagnostics 6.1.8. Intel Agilex EMIF IP DDR4 Parameters: Example Designs
6.4. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning x
6.4.1. Intel® Agilex™ FPGA EMIF IP Interface Pins 6.4.2. Intel® Agilex™ FPGA EMIF IP Resources 6.4.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP
6.4.1. Intel® Agilex™ FPGA EMIF IP Interface Pins x
6.4.1.1. Estimating Pin Requirements 6.4.1.2. DIMM Options 6.4.1.3. Maximum Number of Interfaces
6.4.2. Intel® Agilex™ FPGA EMIF IP Resources x
6.4.2.1. OCT 6.4.2.2. PLL
6.4.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP x
6.4.3.1. Intel® Agilex™ FPGA EMIF IP Banks 6.4.3.2. General Guidelines 6.4.3.3. x4 DIMM Implementation 6.4.3.4. Specific Pin Connection Requirements 6.4.3.5. Command and Address Signals 6.4.3.6. Clock Signals 6.4.3.7. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.5. DDR4 Board Design Guidelines x
6.5.1. Terminations for DDR4 with Intel® Agilex™ Devices 6.5.2. Clamshell Topology 6.5.3. General Layout Routing Guidelines 6.5.4. Reference Stackup 6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies 6.5.7. Intel® Agilex™ EMIF Pin Swapping Guidelines
6.5.1. Terminations for DDR4 with Intel® Agilex™ Devices x
6.5.1.1. Dynamic On-Chip Termination (OCT) 6.5.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.5.1.3. Choosing Terminations on Intel® Agilex™ FPGA Devices 6.5.1.4. On-Chip Termination Recommendations for Intel® Agilex™ FPGA Devices
6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.5.5.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, LRDIMM, and SODIMM DDR4 Topologies 6.5.5.2. Two DIMMs per Channel (2DPC) for UDIMM, RDIMM, and LRDIMM DDR4 Topologies 6.5.5.3. Two DIMMs per Channel (2DPC) for SODIMM Topology 6.5.5.4. Skew Matching Guidelines for DIMM Configurations 6.5.5.5. Power Delivery Recommendations for the Memory / DIMM Side
6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.5.6.1. Single Rank x 8 Discrete (Component) Topology 6.5.6.2. Single Rank x 16 Discrete (Component) Topology 6.5.6.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and R Rank x 16 Discrete (Component) Topologies 6.5.6.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.5.6.5. Power Delivery Recommendations for DDR4 Discrete Configurations
7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support x
7.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions 7.2. Intel® Agilex™ External Memory Interfaces Intel® Calibration IP Parameters 7.3. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning 7.4. QDR-IV Board Design Guidelines
7.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions x
7.1.1. Intel Agilex EMIF IP QDR-IV Parameters: General 7.1.2. Intel Agilex EMIF IP QDR-IV Parameters: Memory 7.1.3. Intel Agilex EMIF IP QDR-IV Parameters: FPGA I/O 7.1.4. Intel Agilex EMIF IP QDR-IV Parameters: Mem Timing 7.1.5. Intel Agilex EMIF IP QDR-IV Parameters: Controller 7.1.6. Intel Agilex EMIF IP QDR-IV Parameters: Diagnostics 7.1.7. Intel Agilex EMIF IP QDR-IV Parameters: Example Designs
7.3. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning x
7.3.1. Intel® Agilex™ FPGA EMIF IP Interface Pins 7.3.2. Intel® Agilex™ FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP
7.3.1. Intel® Agilex™ FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. Maximum Number of Interfaces
7.3.2. Intel® Agilex™ FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP x
7.3.3.1. Intel® Agilex™ FPGA EMIF IP Banks 7.3.3.2. General Guidelines 7.3.3.3. QDR IV SRAM Commands and Addresses, AP, and AINV Signals 7.3.3.4. QDR IV SRAM Clock Signals 7.3.3.5. QDR IV SRAM Data, DINV, and QVLD Signals 7.3.3.6. Specific Pin Connection Requirements 7.3.3.7. Resource Sharing Guidelines (Multiple Interfaces)
7.4. QDR-IV Board Design Guidelines x
7.4.1. General Layout Routing Guidelines 7.4.2. Reference Stackup 7.4.3. Routing Guidelines for QDR-IV Topology 7.4.4. Intel® Agilex™ EMIF Design Guideline Summary
7.4.3. Routing Guidelines for QDR-IV Topology x
7.4.3.1. QDR-IV Single Device Memory Topology 7.4.3.2. Skew Matching Guidelines for QDR-IV Configurations 7.4.3.3. Power Delivery Recommendation for QDR-IV Configurations
8. Intel® Agilex™ FPGA EMIF IP – Timing Closure x
8.1. Timing Closure 8.2. Optimizing Timing
8.1. Timing Closure x
8.1.1. Timing Analysis
8.1.1. Timing Analysis x
8.1.1.1. PHY or Core
9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure x
9.1. I/O Timing Closure Overview 9.2. Collateral Generated with Your EMIF IP 9.3. SPICE Decks 9.4. File Organization 9.5. Top-level Parameterization File 9.6. IP-Supplied Parameters that You Might Need to Override 9.7. Multi-Rank Topology 9.8. Pin Parasitics 9.9. Mask Evaluation
9.3. SPICE Decks x
9.3.1. Address/Command Simulation Deck 9.3.2. FPGA Write Operation Simulation Deck 9.3.3. FPGA Read Operation Simulation Deck
10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Auto-Precharge Commands 10.4.2. Additive Latency 10.4.3. Bank Interleaving 10.4.4. Additive Latency and Bank Interleaving 10.4.5. User-Controlled Refresh 10.4.6. Frequency of Operation 10.4.7. Series of Reads or Writes 10.4.8. Data Reordering 10.4.9. Starvation Control 10.4.10. Command Reordering 10.4.11. Bandwidth 10.4.12. Enable Command Priority Control 10.4.13. Controller Pre-pay and Post-pay Refresh (DDR4 Only)
10.4.1. Auto-Precharge Commands x
10.4.1.1. Using Auto-precharge to Achieve Highest Memory Bandwidth for DDR4 Interfaces
11. Intel® Agilex™ FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Hardware Debugging Guidelines 11.6. Categorizing Hardware Issues 11.7. Debugging with the External Memory Interface Debug Toolkit 11.8. Using the Default Traffic Generator 11.9. Using the Configurable Traffic Generator (TG2) 11.10. EMIF On-Chip Debug Port 11.11. Efficiency Monitor
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages 11.2.4. Modifying the Example Driver to Replicate the Failure
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer x
11.4.1. Signals to Monitor with the Signal Tap Logic Analyzer
11.5. Hardware Debugging Guidelines x
11.5.1. Create a Simplified Design that Demonstrates the Same Issue 11.5.2. Measure Power Distribution Network 11.5.3. Measure Signal Integrity and Setup and Hold Margin 11.5.4. Vary Voltage 11.5.5. Operate at a Lower Speed 11.5.6. Determine Whether the Issue Exists in Previous Versions of Software 11.5.7. Determine Whether the Issue Exists in the Current Version of Software 11.5.8. Try A Different PCB 11.5.9. Try Other Configurations 11.5.10. Debugging Checklist
11.6. Categorizing Hardware Issues x
11.6.1. Signal Integrity Issues 11.6.2. Hardware and Calibration Issues
11.6.1. Signal Integrity Issues x
11.6.1.1. Characteristics of Signal Integrity Issues 11.6.1.2. Evaluating Signal Integrity Issues
11.6.1.2. Evaluating Signal Integrity Issues x
11.6.1.2.1. Skew 11.6.1.2.2. Crosstalk 11.6.1.2.3. Power System 11.6.1.2.4. Clock Signals 11.6.1.2.5. Address and Command Signals 11.6.1.2.6. Read Data Valid Window and Eye Diagram 11.6.1.2.7. Write Data Valid Window and Eye Diagram 11.6.1.2.8. OCT and ODT Usage
11.6.2. Hardware and Calibration Issues x
11.6.2.1. Postamble Timing Issues and Margin 11.6.2.2. Intermittent Issue Evaluation
11.7. Debugging with the External Memory Interface Debug Toolkit x
11.7.1. Prerequisites for Using the EMIF Debug Toolkit 11.7.2. Configuring a Design to Use the Toolkit 11.7.3. Launching the EMIF Debug Toolkit 11.7.4. Using the EMIF Debug Toolkit 11.7.5. Exporting Tables 11.7.6. Viewing Reports Graphically in the Eye Viewer
11.7.2. Configuring a Design to Use the Toolkit x
11.7.2.1. Generating a Design Example with the Debug Toolkit 11.7.2.2. Creating a Design Example with Multiple External Memory Interfaces 11.7.2.3. Enabling the EMIF Toolkit in an Existing Design
11.7.4. Using the EMIF Debug Toolkit x
11.7.4.1. Memory Configuration Tab 11.7.4.2. Calibration Tab 11.7.4.3. Guidelines for Debugging Calibration Issues 11.7.4.4. Calibration Report Tab 11.7.4.5. Calibrate Termination Tab 11.7.4.6. Vref Margining Tab 11.7.4.7. Driver Margining Tab 11.7.4.8. ISSPs Tab 11.7.4.9. Pin Delay Settings Tab
11.7.4.2. Calibration Tab x
11.7.4.2.1. Rerunning Calibration 11.7.4.2.2. Rerunning the Traffic Generator
11.7.4.3. Guidelines for Debugging Calibration Issues x
11.7.4.3.1. Debugging Calibration Failure Using Information from the Calibration report 11.7.4.3.2. Debugging Address and Command Leveling Calibration Failure 11.7.4.3.3. Debugging Address and Command Deskew Failure 11.7.4.3.4. Debugging DQS Enable Failure 11.7.4.3.5. Debugging Read Deskew Calibration Failure 11.7.4.3.6. Debugging VREFIN Calibration Failure 11.7.4.3.7. Debugging LFIFO Calibration Failure 11.7.4.3.8. Debugging Write Leveling Failure 11.7.4.3.9. Debugging Write Deskew Calibration Failure 11.7.4.3.10. Debugging VREFOUT Calibration Failure
11.8. Using the Default Traffic Generator x
11.8.1. Reading the Default Traffic Generator Status 11.8.2. Running Infinite Traffic using the Default Traffic Generator 11.8.3. Changing the Reset Trigger of the Default Traffic Generator 11.8.4. Observing Generated Traffic with Signal Tap
11.9. Using the Configurable Traffic Generator (TG2) x
11.9.1. Enabling the Traffic Generator in a Design Example 11.9.2. Traffic Generator Block Description 11.9.3. Default Traffic Pattern 11.9.4. Configuration and Status Registers 11.9.5. User Pattern 11.9.6. Traffic Generator Status 11.9.7. Starting Traffic with the Traffic Generator 11.9.8. Traffic Generator Configuration User Interface
11.9.5. User Pattern x
11.9.5.1. Test Duration / Instruction pattern 11.9.5.2. Address Pattern 11.9.5.3. Data Pattern and Byte Enable
11.9.5.2. Address Pattern x
11.9.5.2.1. Address Generator Modes 11.9.5.2.2. Address Generator MSB Indices 11.9.5.2.3. Address Generator Effective Width 11.9.5.2.4. Address Generator Relative Frequencies 11.9.5.2.5. Address Pattern Examples - Basic Mode 11.9.5.2.6. Address Pattern Examples - Advanced Mode
11.9.8. Traffic Generator Configuration User Interface x
11.9.8.1. Connecting the Traffic Generator 11.9.8.2. Configuring the Traffic Generator 11.9.8.3. Traffic Generator Preset Selection 11.9.8.4. Traffic Generator Status Report 11.9.8.5. Examples of Configuring the TG2 Traffic Generator
11.10. EMIF On-Chip Debug Port x
11.10.1. Enabling the On-Chip Debug Port 11.10.2. I/O SSM calbus Bridge Data Structures and Usage 11.10.3. I/O SSM User-RAM Data Structures and Usage 11.10.4. Debug Interface Structure 11.10.5. Example: Reading Calibration Results and Margins with the On-Chip Debug Port
11.10.3. I/O SSM User-RAM Data Structures and Usage x
11.10.3.1. Parameter Tables 11.10.3.2. Parameter Table Enums
11.10.3.1. Parameter Tables x
11.10.3.1.1. Global Parameter Table 11.10.3.1.2. Per-interface Parameter Table Structure 11.10.3.1.3. Parameter Table Arrays
11.10.4. Debug Interface Structure x
11.10.4.1. Debug Data Structures 11.10.4.2. Debug Enums
11.11. Efficiency Monitor x
11.11.1. Enabling the Efficiency Monitor in a Design Example 11.11.2. Efficiency Monitor Block Descriptions 11.11.3. Control and Status Registers 11.11.4. Opening the Efficiency Monitor Toolkit
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP
2. Intel® Agilex™ FPGA EMIF IP – Introduction
3. Intel® Agilex™ FPGA EMIF IP – Product Architecture
4. Intel® Agilex™ FPGA EMIF IP – End-User Signals
5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP
6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support
7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support
8. Intel® Agilex™ FPGA EMIF IP – Timing Closure
9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure
10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization
11. Intel® Agilex™ FPGA EMIF IP – Debugging
12. External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives
13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.10.04 21.3  
  • In the Architecture chapter:
  • In the Simulating chapter, changed Mentor Graphics to Siemens EDA, and ModelSim - Intel FPGA Edition to Questa - Intel FPGA Edition.
  • In the DDR4 chapter:
    • Modified the Example Designs with Multi-IPs table in the Intel Agilex EMIF IP DDR4 Parameters: Example Designs topic.
    • Added Register Map IP-XACT Support for Intel Agilex EMIF DDR4 IP topic.
    • Added a note to step 9 in the General Guidelines topic in the Pin Guidelines section.
    • In the Skew Matching Guidelines for DIMM Configurations topic, added two rows to .
    • In the Skew Matching Guidelines for DDR4 Discrete Configurations topic, added two rows to .
  • In the Controller Optimization chapter, added the Controller Pre-pay and Post-pay Refresh (DDR4 Only) topic.
  • In the Debugging chapter:
    • In the Configuration and Status Registers topic, updated .
    • Updated the Address Pattern topic.
    • Updated the Address Pattern topic and added several new topics:
      • Address Generator Modes
      • Address Generator MSB Indices
      • Address Generator Effective Width
      • Address Generator Relative Frequencies
      • Address Pattern Examples - Basic Mode
      • Address Pattern Examples - Advanced Mode
    • In the Traffic Generator Status topic, updated .
    • In the Configuring the Traffic Generator topic, updated the Configurations Tab figure, and added several new figures.
2021.07.09 21.2 2.4.2 In the Debugging chapter, modified the Code Value column in the Error Codes table in the Traffic Generator Status topic.
2021.06.21 21.2 2.4.2
  • In the Architecture chapter,
    • Added the Calibration Algorithms section.
    • Added information to the ECC Support description in the table in the Hard Memory Controller Features topic.
    • Added information to the ECC Controller description in the table in the Hard Memory Controller Main Control Path topic.
  • In the Simulation chapter, added information to the Skip Calibration Mode description in the Calibration Modes topic.
  • In the Debugging chapter:
    • Added Guidelines for Debugging Calibration Issues to the Using the EMIF Debug Toolkit section.
    • Added descriptions of the TG_VERSION and TG_START registers to the table in the Configuration and Status Registers topic.
    • Modified a sentence in the User Traffic section of the Starting Traffic with the Traffic Generator topic.
    • Added the Examples of Configuring the TG2 Traffic Generator topic.
2021.03.29 21.1 2.4.0
  • In the End-User Signals chapter, removed references to Ping-Pong PHY from the port descriptions in the Interface: ctrl_ecc_status table.
  • In the Product Architecture chapter:
    • In the I/O Bank topic, added I/O chaining diagrams for R29A, R31B, and R31C package devices.
    • In the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic, added three rows to the DDRx72 EMIF With AVST and Address/Command Scheme with 4 I/O Lanes table.
  • In the DDR4 chapter, removed a redundant paragraph from the Data, Data Strobes, DM/DBI, and Optional ECC Signals topic.
  • In the Debugging chapter:
    • In Table 154. Configuration and Status Registers, modified the TG_CLEAR register description, and added three additional rows at the bottom of the table.
    • In Table 156. Error Codes, added an additional row to the bottom of the table, for the ERR_BURSTLENGTH_OVERFLOW_ON_FIRST_WRITE code name.
    • In the Traffic Generator Status Report topic:
      • Replaced the figure TG Status Report (Passing Traffic Pattern).
      • Replaced the figure TG Status Report (Failing Traffic Pattern).
      • Replaced the figure TG Status Report (While Running Infinite Traffic).
      • Added the figure TG Status Report (Attempt to Overflow Address Space).
    • In the Control and Status Registers table, changed the register name for the 0x40 entry.
2021.01.20 20.4 2.3.0
  • In the DDR4 chapter, added the Group: Example Designs / Example Design with Multi-IPs table to the Intel Agilex EMIF IP DDR4 Parameters: Example Designs topic.
2020.12.14 20.4 2.3.0
  • In the Product Architecture chapter, recast the text around the table in the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic.
  • In the End-User Signals chapter, removed the AFI Signals and AFI 4.0 Timing Diagrams sections.
  • In the DDR4 chapter:
    • Modified the x4 DIMM Implementation topic.
    • Modified the ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and R Rank x 16 Discrete (Component) Topologies topic.
  • In the Debugging chapter:
    • Replaced the Adding Interfaces to a Design Example topic with Creating a Design Example with Multiple EMIF Interfaces.
    • Replaced the Using the Traffic Generator with the Generated Design Example topic with the Using the Default Traffic Generator section.
    • Retitled the Configurable Traffic Generator (TG2) section to Using the Configurable Traffic Generator (TG2).
2020.10.05 20.3 2.3.0
  • In the About chapter, updated the Release Information topic.
  • In the Product Architecture chapter, added device packages to the I/O Bank topic, and expanded the table in the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic.
  • In the MMR Tables section of the End-User Signals chapter, added ECC error information to the ecc6: Address of Most Recent Correction Command Dropped topic.
  • In the Timing Closure chapter, made a minor addition to the first sentence.
  • Added the Intel® Agilex™ FPGA EMIF IP – Timing Closure chapter.
  • In the Debugging chapter, made changes to the following:
    • In the Debugging with the External Memory Interface Debug Toolkit section, made changes to the following topics:
      • Rerunning the Traffic Generator (added information on changing address ordering)
      • Calibration Report Tab
      • Calibrate Termination Tab (recast text and added image)
      • ISSPs Tab (added row to bottom of table)
      • Viewing Reports Graphically in the Eye Viewer (added an additional eye diagram)
    • In the Configurable Traffic Generator (TG2) Description section, made changes to the following topics:
      • Enabling the Traffic Generator in a Design Example
      • Configuration and Status Registers (changed description of TG_TEST_BYTEEN register)
      • Configuring the Traffic Generator (updated images)
      • Traffic Generator Preset Selection (new topic)
      • Traffic Generator Status Report (updated images)
    • In the On-Chip Debug Port section, made changes to the following topics:
      • I/O SSM calbus Bridge Data Structures and Usage (added note and figure, modified DQS Tree Structure table)
      • Parameter Table Arrays (modified 2 (DQS_C) entry in Example table)
      • Debug Data Structures (modified cur_interface_idx entry in the mem_summary_report table, and corrected text in debug_cal_data_struct section.
      • Example: Reading Calibration Results and Margins with the On-Chip Debug Port
    • In the Efficiency Monitor section, made changes to the following topics:
      • Enabling the Efficiency Monitor in a Design Example (updated second bullet and image)
      • Control and Status Registers (updated last row in table)
      • Opening the Efficiency Monitor Toolkit (updated images)
2020.06.22 20.2 2.2.0
  • In the Product Architecture chapter, made minor changes to the Intel® Agilex™ Calibration Stages and Intel® Agilex™ Calibration Algorithms topics.
  • In the Functional Simulation chapter, added text and a figure to the Simulation Walkthrough topic.
  • In the Debugging chapter, updated images throughout the Debugging with the External Memory Interface Debug Toolkit section.
  • In the Debugging chapter, made several changes to the Configurable Traffic Generator (TG2) section:
    • Minor change to terminology in the Default Traffic Pattern, Configuration and Status Registers, Test Duration / Instruction Pattern, and Address Pattern topics.
    • Expanded content in the Starting Traffic with the Traffic Generator topic.
    • Updated images in the Configuring the Traffic Generator and Traffic Generator Status Report topics.
  • In the Debugging chapter, added the EMIF On-chip Debug Port section.
2020.04.27 20.1 2.1.0
  • In the DDR4 chapter, modified guidelines 2 and 3, and added guideline 11, in the General Guidelines topic.
  • In the QDR-IV chapter:
    • Modified guidelines 2 and 3, and added guideline 11, in the General Guidelines topic.
    • Added guideline 4 to the I/O Bank section of the Resource Sharing Guidelines (Multiple Interfaces) topic.
2020.04.13 20.1 2.1.0
  • In the Introduction chapter:
    • Added QDR-IV support to the Intel® Agilex™ EMIF IP Protocol and Feature Support topic.
    • Added links to QDR-IV Parameter Descriptions to the Intel® Agilex™ EMIF IP Design Checklist topic.
  • In the Architecture chapter:
    • Added QDR-IV support to the Introduction topic.
  • In the End-User Signals chapter:
    • Added QDR-IV interfaces and signals to the Interface and Signal Descriptions section.
    • In the AFI 4.0 Timing Diagrams section, removed Write data sequence with CRC.
    • Implemented changes to the ctrlcfg1, sbcfg1, and caltiming4 tables in the Memory Mapped Register (MMR) Tables section.
  • Added the Intel® Agilex™ FPGA EMIF IP – QDR-IV Support chapter.
  • In the Debugging chapter:
    • Implemented numerous changes to the Debugging with the External Memory Interface Debug Toolkit section.
    • Added the Configurable Traffic Generator (TG2) Description section.
2020.02.10 19.4 2.0.0
  • In the DDR4 chapter:
    • Added the x4 DIMM Implementation topic to the Pin and Resource Planning section.
    • Added the Clamshell Topology topic to the DDR4 Board Design Guidelines section.
  • In the Debugging chapter, modified the last sentence of the Intermittent Issue Evaluation topic.
2019.12.16 19.4 2.0.0
  • In the Architecture chapter:
    • Modified the first sentence following Figure 7 in the I/O Bank topic.
    • Added the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic.
  • In the DDR4 chapter:
    • Expanded the DDR4 Board Design Guidelines section.
  • In the Debugging chapter:
    • Added the Debugging With the External Memory Interface Debug Toolkit section.
  • Added External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives topic.
2019.10.18 19.3  
  • In the Introduction chapter, revised the EMIF IP Design Flow flowchart.
  • In the Product Architecture chapter:
    • Updated the Intel Agilex I/O Subsystem figure in the EMIF Architecture: I/O Subsystem topic.
    • Modified the first paragraph, and updated the connectivity diagrams in the EMIF Architecture: I/O SSM topic.
    • Modified the Pin Index Mapping table in the EMIF Architecture: I/O Lane topic.
    • Added an explanation of Quasi-1T to the description of the Arbiter component in the Main Control Path Components table in the Hard Memory Controller Main Control Path topic.
    • Removed the note from the beginning of the Intel® Agilex™ EMIF for Hard Processor Subsystem topic.
  • In the DDR4 Support chapter:
    • Removed the Board Skew Equations section.
    • Modified entries for the Clock pin in the UDIMM, RDIMM, and LRDIMM Pin Options for DDR4 table.
    • Removed the Channel Signal Integrity Measurement and Package Deskew sections.
  • In the Timing Closure chapter:
    • Modified the Core to periphery (C2P) and Periphery to core (P2C) descriptions in the Timing Closure topic.
    • Removed references to Early I/O Timing Estimation.
  • In the Controller Optimization chapter:
    • In the Bank Interleaving topic, modified the names of the three supported interleaving options.
    • Added content to the paragraph introducing the examples, in the Using Auto-precharge to Achieve Highest Memory Bandwidth for DDR4 Interfaces topic.
  • In the Debugging chapter:
    • Added the Debugging with the External Memory Interface Debug Toolkit section.
    • Added the Using the Traffic Generator with the Generated Design Example topic.
2019.07.31 19.2 1.2.0
  • Added the About the External Memory Interfaces Intel® Agilex™ FPGA IP chapter.
  • In the topic Intel® Agilex™ EMIF for Hard Processor Subsystem, in the Product Architecture chapter, changed the description of Memory format in the table from 16GB support to 32GB support.
  • In the Intel® Agilex™ FPGA EMIF IP — End-User Signals chapter:
    • Removed emif_usr_reset_n_sec and emif_usr_clk_sec from Table 10, Interfaces for DDR4.
    • In the topic 3.1.1.10, mem for DDR4, modified the description of mem_a in the table.
    • Removed the 3.1.1.18 emif_usr_reset_n_sec for DDR4 and 3.1.1.19 emif_usr_clk_sec for DDR4 topics.
    • Removed sbcfg1, sideband2, sideband3, sideband5, sideband8, sideband10, and sideband15 from the Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables.
    • Changed the Bit High value for the second row in the dramtiming0 MMR table.
    • Changed the Field name and Description text for the fourth row in the caltiming4 MMR table.
    • Made several changes in the Description column of the sideband13 MMR table.
    • Changed the Field, Bit High, Bit Low, and Description values in the sideband14 MMR table.
  • In the Intel® Agilex™ EMIF IP DDR4 Parameters: Memory topic of the DDR4 chapter:
    • Removed the Enable ALERT#/PAR pins parameter and recast the description of the ALERT# pin placement parameter in the Group: Memory / Topology table.
  • In the Intel® Agilex™ EMIF IP DDR4 Parameters: Mem I/O topic, revised the description for the SPD Byte 145-147 - DB MDQ Drive Strength and RTT parameter.
  • In the Intel® Agilex™ EMIF IP DDR4 Parameters: Diagnostics topic:
    • Added the Group: Diagnostics / Example Design table.
    • Added the Group: Diagnostics / Traffic Generator table (marked as future support).
    • Added the Group: Diagnostics / Performance and Group: Diagnostics / Miscellaneous tables.
  • Added the Intel® Agilex™ EMIF IP DDR4 Parameters: Example Designs topic.
  • In the Intel® Agilex™ FPGA EMIF IP — Timing Closure chapter, revised the Optimizing Timing topic.
  • Removed occurrences of Ping Pong PHY throughout.
2019.04.02 19.1  
  • Initial release.
Level Two Title