External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1.18. ctrl_user_priority for DDR4

Controller user-requested priority interface

Table 31.  Interface: ctrl_user_priorityInterface type: Conduit
Port Name Direction Description
ctrl_user_priority_hi Input When asserted high along with a read or write request to the memory controller, indicates that the request is high priority and should be fulfilled before other low priority requests.