External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

11.6.1.2.5. Address and Command Signals

Confirm that address and command signals are reaching the memory devices correctly.

After the memory interface has been successfully calibrated, you can probe the ALERT_N pin to determine if any memory component has encountered an address and command parity error.