External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

11.7.4.1. Memory Configuration Tab

The Memory Configuration tab shows the IP settings, which were defined when you parameterized the EMIF IP.

Figure 119. Memory Configuration Tab