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3.5. Verifying I/O Timing
For example, if you change the slew rates or drive strengths of some I/O pins with ECOs, you can verify timing without recompiling the design. You must understand I/O timing and what factors affect I/O timing paths in your design. The accuracy of the output load specification of the output and bidirectional pins affects the I/O timing results.
The Intel® Quartus® Prime software supports three different methods of I/O timing analysis:
I/O Timing Analysis |
Description |
---|---|
Advanced I/O timing analysis |
Analyze I/O timing with your board trace model to report accurate, “board-aware” simulation models. Configures a complete board trace model for each I/O standard or pin. Timing Analyzer applies simulation results of the I/O buffer, package, and board trace model to generate accurate I/O delays and system level signal information. Use this information to improve timing and signal integrity. |
I/O timing analysis |
Analyze I/O timing with default or specified capacitive load without signal integrity analysis. Timing Analyzer reports tCO to an I/O pin using a default or user-specified value for a capacitive load. |
Full board routing simulation |
Use Intel-provided or Intel® Quartus® Prime software-generated IBIS or HSPICE I/O models for simulation in Mentor Graphics* HyperLynx* and Synopsys* HSPICE. |
For more information about advanced I/O timing support, refer to the appropriate device handbook for your target device. For more information about board-level signal integrity and tips on how to improve signal integrity in your high-speed designs, refer to the Signal Integrity and Power Integrity – Support Center website.
For information about creating IBIS and HSPICE models with the Intel® Quartus® Prime software and integrating those models into HyperLynx* and HSPICE simulations, refer to the Signal Integrity Analysis with Third Party Tools chapter.