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1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.5. Adjust Constraints with the Chip Planner
1.1.2.6. Constraining Designs with the Design Partition Planner
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2.2.2.6. Step 6: Run Logic Generation and Design Synthesis
After saving your tile plan assignments, run the Compiler's Logic Generation stage to implement your tile plan and continue synthesis and the remaining design compilation stages.
To run Logic Generation and design synthesis, follow these steps:
- Save your tile interface plan, as Step 5: Save Tile Plan Assignments describes.
- In the Intel® Quartus® Prime software, double-click the Logic Generation stage in the Compilation Dashboard. Logic Generation reads the tile plan assignments from the .qsf.
Figure 41. Run Logic Generation Stage Before Synthesis
- When Logic Generation is complete, double-click Analysis & Synthesis on the Compilation Dashboard.
- When Analysis & Synthesis is complete, you can run the other remaining downstream stages in the compilation flow when ready.