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1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.5. Adjust Constraints with the Chip Planner
1.1.2.6. Constraining Designs with the Design Partition Planner
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1.1.2. Node, Entity, and Instance-Level Constraints
Node, entity, and instance-level constraints apply to a subset of the design hierarchy. These constraints take precedence over any global assignment that affects the same sections of the design hierarchy. The following tools are available in the Intel® Quartus® Prime software to specify node, entity, and instance-level constraints:
Assignment Type | Assignment Editor | Interface Planner | Chip Planner | Pin Planner |
---|---|---|---|---|
Pin | X | X | ||
Location | X | X | X | |
Routing | X | X | ||
Simulation | X | X | X |
Although you can specify constraints using a variety of tools, the following table shows the most effective constraint tools at each design phase:
Design Phase | Assignment Editor | Interface Planner | Tile Interface Planner | Chip Planner | Timing Analyzer | Pin Planner |
---|---|---|---|---|---|---|
Pre-Synthesis | X | X | X | |||
Post-Synthesis | X | X | X | |||
Post-Fit | X | X | X |
- Specify Instance-Specific Constraints in Assignment Editor
- Specifying Multi-Dimensional Bus Constraints
- Specify I/O Constraints in Pin Planner
- Plan Interface Constraints in Interface Planner and Tile Interface Planner
- Adjust Constraints with the Chip Planner
- Constraining Designs with the Design Partition Planner