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1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.5. Adjust Constraints with the Chip Planner
1.1.2.6. Constraining Designs with the Design Partition Planner
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3. Managing Device I/O Pins
This chapter describes efficient planning and assignment of I/O pins in your target device. Consider I/O standards, pin placement rules, and your PCB characteristics early in the design phase.
Figure 43. Pin Planner GUI
I/O Planning Task |
Click to Access |
---|---|
Plan interfaces and device periphery | Tools > Interface Planner |
Edit, validate, or export pin assignments |
Assignments > Pin Planner |
For more information about special pin assignment features for the Intel® Arria® 10 SoC devices, refer to Instantiating the HPS Component in the Intel® Arria® 10 Hard Processor System Technical Reference Manual.