Visible to Intel only — GUID: mqd1570553666787
Ixiasoft
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.5. Adjust Constraints with the Chip Planner
1.1.2.6. Constraining Designs with the Design Partition Planner
Visible to Intel only — GUID: mqd1570553666787
Ixiasoft
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
The Intel® Quartus® Prime Pro Edition software traditionally supports only 1- and 2-dimensional bus names for specifying constraints. The Intel® Quartus® Prime Pro Edition version 19.3 and later now supports multi-dimensional bus names for more efficient constraints.
For example, you can specify the following assignment to apply a constraint to all bits in the reg [31:0] r [0:2][4:5] three-dimensional bus:
set_instance_assignment -name PRESERVE_REGISTER ON -to r
The constraint then applies to all bits r: [0][4][31], r[0][4][30], … , r[1][5][0].