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1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.5. Adjust Constraints with the Chip Planner
1.1.2.6. Constraining Designs with the Design Partition Planner
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3.1.1. Basic I/O Planning Flow
The following steps describe the basic flow for assigning and verifying I/O pin assignments:
- Click Assignments > Device and select a target device that meets your logic, performance, and I/O requirements. Consider and specify I/O standards, voltage and power supply requirements, and available I/O pins.
- Click Assignments > Pin Planner.
- Assign I/O properties to match your device and PCB characteristics, including assigning logic, I/O standards, output loading, slew rate, and current strength.
- Click Run I/O Assignment Analysis in the Tasks pane to validate assignments and generate a synthesized design netlist. Correct any problems reported.
- Click Processing > Start Compilation. During compilation, the Intel® Quartus® Prime software runs I/O assignment analysis.