Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

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ID 683143
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Constraining Designs 2. Interface Planning 3. Managing Device I/O Pins 4. Intel® Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints Designs in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints Designs in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Intel® Quartus® Prime GUI 1.1.4. Specifying Timing Constraints in the GUI
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specifying Multi-Dimensional Bus Constraints 1.1.2.3. Specify I/O Constraints in Pin Planner 1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner 1.1.2.5. Adjust Constraints with the Chip Planner 1.1.2.6. Constraining Designs with the Design Partition Planner
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Intel® Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows
2. Interface Planning x
2.1. Using Interface Planner 2.2. Using Tile Interface Planner 2.3. Interface Planning Revision History
2.1. Using Interface Planner x
2.1.1. Interface Planner User Interface 2.1.2. Interface Planner Tool Flow 2.1.3. Interface Planner Reports
2.1.1. Interface Planner User Interface x
2.1.1.1. Flow Controls 2.1.1.2. Home Tab Controls 2.1.1.3. Assignments Tab Controls 2.1.1.4. Plan Tab Controls 2.1.1.5. Reports Tab Controls
2.1.2. Interface Planner Tool Flow x
2.1.2.1. Step 1: Setup and Synthesize the Project 2.1.2.2. Step 2: Initialize Interface Planner 2.1.2.3. Step 3: Update Plan with Project Assignments 2.1.2.4. Step 4: Plan Periphery Placement 2.1.2.5. Step 5: Report Placement Data 2.1.2.6. Step 6: Validate and Export Plan Constraints
2.1.2.4. Step 4: Plan Periphery Placement x
2.1.2.4.1. Plan Clock Networks 2.1.2.4.2. Saving & Loading Floorplans
2.1.3. Interface Planner Reports x
2.1.3.1. Report Summary 2.1.3.2. Report Pins 2.1.3.3. Report HSSI Channels 2.1.3.4. Report Clocks 2.1.3.5. Report Periphery Locations 2.1.3.6. Report Cell Connectivity 2.1.3.7. Report Instance Assignments
2.2. Using Tile Interface Planner x
2.2.1. Tile Interface Planner Terminology 2.2.2. Tile Interface Planner Tool Flow 2.2.3. Tile Interface Planner GUI Reference
2.2.2. Tile Interface Planner Tool Flow x
2.2.2.1. Step 1: Instantiate IP and Run Design Analysis 2.2.2.2. Step 2: Initialize Tile Interface Planner 2.2.2.3. Step 3: Update Plan with Project Assignments 2.2.2.4. Step 4: Create a Tile Plan 2.2.2.5. Step 5: Save Tile Plan Assignments 2.2.2.6. Step 6: Run Logic Generation and Design Synthesis
2.2.2.4. Step 4: Create a Tile Plan x
2.2.2.4.1. Placing IP Components 2.2.2.4.2. Constraining IP Building Blocks 2.2.2.4.3. Multi-Rate IP Tile Planning
2.2.3. Tile Interface Planner GUI Reference x
2.2.3.1. Flow Controls 2.2.3.2. Home Tab 2.2.3.3. Assignments Tab Controls 2.2.3.4. Plan Tab Controls 2.2.3.5. Tcl Console Window
2.2.3.4. Plan Tab Controls x
2.2.3.4.1. Design Tree and Filters 2.2.3.4.2. Legal Locations Pane
3. Managing Device I/O Pins x
3.1. I/O Planning Overview 3.2. Assigning I/O Pins 3.3. Importing and Exporting I/O Pin Assignments 3.4. Validating Pin Assignments 3.5. Verifying I/O Timing 3.6. Viewing Routing and Timing Delays 3.7. Scripting API 3.8. Managing Device I/O Pins Revision History
3.1. I/O Planning Overview x
3.1.1. Basic I/O Planning Flow 3.1.2. Integrating PCB Design Tools 3.1.3. Intel Device Terms
3.2. Assigning I/O Pins x
3.2.1. Assigning to Exclusive Pin Groups 3.2.2. Assigning Slew Rate and Drive Strength 3.2.3. Assigning Differential Pins 3.2.4. Entering Pin Assignments with Tcl Commands 3.2.5. Entering Pin Assignments in HDL Code
3.2.3. Assigning Differential Pins x
3.2.3.1. Overriding I/O Placement Rules on Differential Pins
3.2.5. Entering Pin Assignments in HDL Code x
3.2.5.1. Using Low-Level I/O Primitives
3.3. Importing and Exporting I/O Pin Assignments x
3.3.1. Importing and Exporting for PCB Tools 3.3.2. Migrating Assignments to Another Target Device
3.4. Validating Pin Assignments x
3.4.1. I/O Assignment Validation Rules 3.4.2. I/O Assignment Analysis 3.4.3. Understanding I/O Analysis Reports
3.4.2. I/O Assignment Analysis x
3.4.2.1. Early I/O Assignment Analysis Without Design Files 3.4.2.2. I/O Assignment Analysis With Design Files 3.4.2.3. Overriding Default I/O Pin Analysis
3.5. Verifying I/O Timing x
3.5.1. Running Advanced I/O Timing 3.5.2. Adjusting I/O Timing and Power with Capacitive Loading
3.5.1. Running Advanced I/O Timing x
3.5.1.1. Board Trace Models 3.5.1.2. Defining the Board Trace Model 3.5.1.3. Modifying the Board Trace Model 3.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 3.5.1.5. Advanced I/O Timing Analysis Reports
3.7. Scripting API x
3.7.1. Generate Mapped Netlist 3.7.2. Reserve Pins 3.7.3. Set Location 3.7.4. Exclusive I/O Group 3.7.5. Slew Rate and Current Strength
1. Constraining Designs
2. Interface Planning
3. Managing Device I/O Pins
4. Intel® Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

2.2.2.4.3. Multi-Rate IP Tile Planning

Tile Interface Planner provides support for tile planning with multi-rate IP components, such as the F-tile CPRI PHY Multi-Rate Intel FPGA IP.

Tile Interface Planner displays the tile location of multi-rate IP and building blocks in your project. Tile Interface Planner shows the initial, read-only multi-rate IP profile as profile_0 in the Design Element hierarchy.

You cannot edit the multi-rate IP tile location in the current version of Tile Interface Planner. However, you can view the multi-rate IP tile location, and then place other IP components in relation to that location.

To perform tile planning with multi-rate IP, follow these steps:
  1. Instantiate and elaborate a multi-rate IP component in your design, as Step 1: Instantiate IP and Run Design Analysis describes.
    Note: Tile Interface Planner currently supports only the F-tile CPRI PHY Multi-Rate Intel FPGA IP for multi-rate tile planning.
  2. Start Tile Interface Planner, as Step 2: Initialize Tile Interface Planner describes.
  3. Update the plan with existing assignments, as Step 3: Update Plan with Project Assignments describes.
  4. In Tile Interface Planner, click the Plan tab. Tile Interface Planner displays the initial, read-only multi-rate IP profile as profile_0 in the Design Element hierarchy. The Placement column is grayed, indicating that the multi-rate IP placement is not editable in the current version of Tile Interface Planner.
    Figure 36. Multi-Rate IP in Tile Interface Planner
  5. Expand the multi-rate IP's "bb_" subfolders to view the multi-rate IP's building blocks for the initial dynamic reconfiguration profile.
    Figure 37. Multi-Rate IP Building Blocks for Initial Multi-Rate Profile
  6. Place other IP components in relation to that location, as Placing IP Components describes.
    Figure 38. Placing Other IP Components
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