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1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.5. Adjust Constraints with the Chip Planner
1.1.2.6. Constraining Designs with the Design Partition Planner
2.2.2.1. Step 1: Instantiate IP and Run Design Analysis
2.2.2.2. Step 2: Initialize Tile Interface Planner
2.2.2.3. Step 3: Update Plan with Project Assignments
2.2.2.4. Step 4: Create a Tile Plan
Recommended Two-Stage Tile IP Placement
2.2.2.5. Step 5: Save Tile Plan Assignments
2.2.2.6. Step 6: Run Logic Generation and Design Synthesis
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2.2.2.4. Step 4: Create a Tile Plan
Click Plan Design on the Flow control to interactively place component IP in legal locations on device tiles. The Plan tab displays a hierarchical list of your project component IP design elements, alongside a graphical abstraction of the target device tile architecture. Place IP (and IP building blocks) in legal tile locations within the graphical tile floorplan.
Tile Interface Planner Design Elements and Chip View
Recommended Two-Stage Tile IP Placement
Handle IP tile placement in two stages for the most efficiency:
Tile IP Placement | Description |
---|---|
Stage 1 |
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Stage 2 |
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Note: Changes made in Tile Interface Planner do not apply to your Intel® Quartus® Prime project until you apply the generated tile interface plan constraints to your project, as Step 5: Save Tile Plan Assignments describes.