FPGA Power Solutions Resources
Power solutions power consumption considerations when planning system designs, estimating and meeting power requirements throughout the entire design flows.
The FPGA Power Solutions provides resources for Agilex™ 7, Agilex™ 5, Stratix® 10, Arria® 10, and Cyclone® 10 devices. These resources will help guide you through power consumption considerations when planning system designs, estimating power requirements throughout the entire design flow, and meeting demanding power requirements using converters. The converters feature integrated inductors to deliver an industry-leading combination of high efficiency, small footprint, and low-noise performance.
Get additional support for Agilex™ 7 Board Design Guided Journey, Agilex™ 5 FPGA Board Design Guided Journey, step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.
For other devices, search the Device and Product Support Collections.
Getting Started
Power system design is done in several logical phases:
Choosing a Power Tree
In this phase, a power tree topology is chosen based on the requirements of the device. The requirements of the power supply may not yet be known, but the supply voltage and connection requirements of various devices are available in the Power Management Handbooks, and Pin Connection Guidelines. Any required power supply sequencing and SmartVID usage will impact the power tree topology.
Power Estimation
In this phase, the amount of electrical power required by the various device power supplies is estimated using the Early Power Estimator (EPE) tool or FPGA Power and Thermal Calculator (PTC) and the Quartus® Prime Power Analyzer tool. As the design evolves to the final configuration, the quality and type of information available improve and the estimation becomes more accurate.
The current version of the FPGA PTC supports Agilex™ and Stratix® 10 devices. This tool does not support older devices such as the Arria® 10 and Cyclone® 10 families; use the corresponding Early Power Estimator if you are working with those devices.
Power Optimization
In this phase, the device configuration can be optimized for minimum power. This step can involve the Quartus® software power optimization wizard, the SmartVID feature (in some devices), system cooling decisions, and/or dynamic workload management strategies. This phase may occur several times during the evolution of the system and device design.
Power Generation
In this phase, voltage regulator modules (VRMs) are selected based on the power tree and electrical power estimations. VRM selection is critical to producing high-quality power systems with the minimum number and cost of bypass elements.
Power Distribution
In this phase, the power distribution network (PDN) is designed, producing a list of the required number, value, and quality of bypass capacitors using the PDN tool, power tree, VRMs, electrical power estimations, and board physical geometries.
Power Dissipation and Thermal Considerations
In this phase, thermal power estimations are used to select device cooling solutions. The EPE or PTC assists with the cooling of system designs. The effects of junction temperature on device power generation and device reliability should be considered in this phase.
1. Power Architecture – The Power Tree
Designing the Power Tree
2. Estimation and Optimization
Power Estimators and User Guides
Calculator
Training and videos
- Power Analysis Training
- Power Supply, Ripple & Load Transient Terms and Correct Way to Measure Ripple
- Exporting Power Parameters Quartus® and Importing Them into the EPE Tool
User Guide
Power Optimization
Application Notes
- AN 711: Power Reduction Features in Arria® 10 Devices
- AN 531: Reducing Power with Hardware Accelerators
Video
FAQ
Additional Resources
Agilex™ 7 Devices
- Agilex™ 7 Power Management User Guide
- Agilex™ 7 Device Family Pin Connection Guidelines
- Agilex™ 7 Device Data Sheet
Agilex™ 5 Devices
- Agilex™ 5 FPGAs and SoCs Power Management User Guide
- Agilex™ 5 Device Family Pin Connection Guidelines
- Agilex™ 5 Device Datasheet
Stratix® 10 Devices
- Stratix® 10 Power Management User Guide
- Stratix® 10 Device Family Pin Connection Guidelines
- Stratix® 10 Device Datasheet
Arria® 10 Devices
- Arria® 10 Core Fabric and General Purpose I/Os Handbook
- Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
- Arria® 10 Device Datasheet
Cyclone® 10 LP Devices
3. Generation and Distribution
Generation
- AN 583: Designing Power Isolation Filters with Ferrite Beads for FPGAs
- AN 692: Power Sequencing Considerations for Agilex™ 7, Agilex™ 5, Stratix® 10, Arria® 10 and Cyclone® 10 GX Devices
- AN 742: PMBus SmartVID Controller Reference Designs
Distribution
- AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology
- AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
- Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
- Power Distribution Network
Additional Resources
4. Power Dissipation and Thermal Management
General
Stratix® 10 Devices
5. User Guides, Checklists, Design Examples, and Reference Designs
User Guides
General
Agilex™ Devices
- Agilex™ 7 Power Management User Guide
- Agilex™ 5 FPGAs and SoCs Power Management User Guide
- FPGA Power and Thermal Calculator User Guide
Stratix® 10 Devices
Arria® 10 Devices
Cyclone® 10 GX Devices
Cyclone® 10 LP Devices
MAX® 10 Devices
Checklists
- SmartVID Debug Checklist for FPGAs
- Early Power Estimator (EPE) and Power and Thermal Calculator (PTC) Debug Checklist
Design Examples and Reference Designs
6. Training Courses and Videos
FPGA Technical Training
Topic |
Description |
|---|---|
This is part one of a two-part training course. This training course will give you the knowledge and tools you need to perform highly accurate power usage estimations using the Quartus® Prime software. In this first part, you’ll learn how to perform an early power estimation before you've even started creating a design. You'll also learn how to set up and use the Power Analyzer to generate detailed reports on both static and dynamic power usage at any stage of the FPGA design flow. |
|
This is part two of a two-part training course. This training will give you the knowledge and tools you need to perform highly accurate power usage estimations using the Quartus® Prime software. In this second part, now that you know how to perform a power analysis, you’ll see how to use this information to optimize a design to minimize power through power-driven compilation options and following low-power design guidelines. |
|
Thermal management is an important aspect of implementing today's high-speed devices. The more power put into a device, the more heat that must be removed. Most FPGA devices consist of a single monolithic silicon die, making the process of designing a cooling solution focused on that single die. Stratix® 10 FPGA devices, however, consist of a core die and multiple transceiver dies, each of which affect the overall thermal profile of the entire device. In this training, you'll learn about the thermal factors involved with a multi-die device and how the new Stratix® 10 Early Power Estimator (EPE) makes it easy to calculate these factors based on your design and transceiver channel use. Use these calculated factors to make decisions about your FPGA design and cooling solution. |
FPGA Quick Videos
Topic |
Description |
|---|---|
Power Supply, Ripple & Load Transient Terms and Correct Way to Measure Ripple |
This short video explains the FPGA power supply deviation nomenclature and how to stay within the static and dynamic power accuracy budget. |
Exporting Power Parameters from Quartus® and Importing Them into the EPE Tool |
This short video introduces the Early Power Estimator (EPE) tool and how to easily export your design from the Quartus® software. |
7. Debug
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