F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 4/03/2024
Public
Document Table of Contents

1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 5.0.0
This user guide provides the features, architecture description, steps to instantiate, and guidelines about the F-Tile Low Latency 50G Ethernet Intel® FPGA IP for the Agilex™ 7 (F-Tile) and Agilex™ 9 (F-Tile) devices.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase