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Ixiasoft
1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile 25G Ethernet Intel FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. F-Tile 25G Ethernet Intel FPGA IP User Guide Archive
10. Document Revision History for the F-Tile 25G Ethernet Intel FPGA IP User Guide
7.1. TX MAC Interface to User Logic
7.2. RX MAC Interface to User Logic
7.3. Transceivers
7.4. Transceiver Reconfiguration Signals
7.5. Avalon® Memory-Mapped Management Interface
7.6. Dynamic Reconfiguration Interface Signals
7.7. Miscellaneous Status and Debug Signals
7.8. Clock Signals
7.9. Reset Signals
Visible to Intel only — GUID: tjj1662695195186
Ixiasoft
1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
Updated for: |
---|
Intel® Quartus® Prime Design Suite 24.2 |
IP Version 6.0.0 |
This user guide provides the features, architecture description, steps to instantiate, and guidelines about the F-Tile 25G Ethernet Intel FPGA IP for the Agilex™ 7 devices.
Intended Audience
This document is intended for:
- Design architect to make IP selection during system level design planning phase
- Hardware designers when integrating the IP into their system level design
- Validation engineers during system level simulation and hardware validation phase
Related Documents
The following table lists other reference documents which are related to the F-Tile 25G Ethernet Intel FPGA IP protocol.
Reference | Description |
---|---|
F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide | Provides information about how to instantiate F-Tile 25G Ethernet Intel FPGA IP design examples using the Agilex™ 7 (F-Tile) devices. |
F-Tile 25G Ethernet Intel FPGA IP Release Notes | Lists the changes made for the F-Tile 25G Ethernet Intel FPGA IP in a particular release. |
F-Tile Ethernet Intel FPGA Hard IP User Guide | Provides the features, architecture description, steps to instantiate, and guidelines about the F-Tile Ethernet Intel FPGA Hard IP User Guide. |
F-Tile Architecture and PMA and FEC Direct PHY IP User Guide | Provides information about the architecture and implementation details for the Agilex™ 7 F-Tile building blocks, physical (PHY) layer IP, PLLs, and clock networks. |
Acronyms and Glossary
Acronym | Expansion |
---|---|
ALM | Adaptive Logic Element |
AVMM | Avalon® memory-mapped interface |
AVST | Avalon® streaming interface |
AXI | ARM corporation's Advanced Extensible Interface |
CRC | Cyclic redundancy code |
CSR | Control and Status Register |
EMIB | Intel Embedded Silicon Bridge technology |
FCQN | Flow Control Queue Number |
FPGA | Field Programmable Gate Array |
LAB | Logic Array Block |
MAC | Media Access Control |
MLAB | Memory Logic Array Block |
PCS | Physical coding sublayer |
PFC | Priority-based flow control |
PHY | Physical layer |
PLL | Phase-locked loop |
PMA | Physical medium attachment |
QN | Queue Number |