OpenCL™ - BSP - Support Center
Product Discontinuance Notice
Intel is discontinuing Intel® FPGA SDK for OpenCL™, more information can be found in product discontinuance notification (PDN2219).
The OpenCL™ BSP support page provides information on how to plan, design, and implement your OpenCL™ BSP, as well as learn a few tips and tricks for debugging purposes.
1. Modify a Reference Design
Getting Started
To get started with the BSP development, ensure that you perform the following steps:
- Confirm that the Intel® FPGA SDK for OpenCL™ and Intel® Quartus® software is installed.
- Verify that the tool version that matches the OpenCL™ reference BSP is available.
- Confirm access to the full Intel® Quartus® software license.
Select a Reference Design
Select the reference design that suits your custom platform
Intel supports the OpenCL™ reference BSP designs for the following platforms. You can also view the OpenCL™ BSP porting guide for a specific platform:
- Stratix® V PCIe* Development Kit - View the Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
- Intel® Arria® 10 PCIe Development Kit - View the Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide
- Intel® Arria® 10 SoC Development Kit - View the Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide
- Intel® Stratix® 10 PCIe* Development Kit - View the Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide
Modify a Reference Design
Start modifying the reference design to your platfrom by following the steps in the OpenCL BSP porting guides. It is recommended that after the design changes are complete, you should try compiling your first kernel. Generally, we use a kernel called Boardtest, which tests out different interfaces of the BSP. Information on the Boardtest and generic BSP building steps are mentioned in the following guide:
Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide (PDF)
Recommended steps to build a BSP:
- Compile the Boardtest in "flat" flow to generate a timing closed ".aocx" file
- Validate the ".aocx" by running the Boardtest and cross-check the interface bandwidth expections from the test
- Start working on floorplanning for "base" build to create a guaranteed timing-closed OpenCL BSP
2. Floorplanning and Timing Closure
Getting Started
In OpenCL, we need to work on the timing for two different revisions of the project – the flat and the base revisions. A flat revision is the one without any partitions or logic lock regions and uses the hardware/flat.qsf file to implement it. While the base revision is the one which includes the partitioning and the logic locks, and uses the hardware/base.qsf file to implement it. We recommend that you get a timing-clean flat revision first as a good start and then work on floorplanning to get a timing-clean base revision of the design.
For more details on the compilation flow, refer the OpenCL™ BSP Compilation Flow section in the Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide.
Floorplan Partition
Begin with flat compilation to understand where all the main components of the BSP gets placed naturally (especially the intellectual property (IP) blocks with I/O connections, such as PCIe* or DDR memory).
For more guidelines on this, refer to the Guidelines for OpenCL™ BSP Floorplanning section in the Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide.
For details, you can also refer to the Partial Reconfiguration User Guide.
Modify PR Region
During base compilation, start with the Logic Lock Region on kernel that contains freeze_wrapper_inst|kernel_system_inst. Use the flat compile and chip planner to identify the size and location of the BSP hardware. Attempt to reserve more resources for the kernel_system by using the Logic Lock Region.
For more guidelines on this, refer to the Guidelines for OpenCL™ BSP Floorplanning section in the Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide.
Fixing Timing Violations
To fix timing violations in the design, you might need to add pipeline stages in between IP cores.
For more guidelines, refer the following links:
Setup/Hold Constraints
The .failing_paths.rpt and .failing_clocks.rpt in the output directory list the major failures in the design. If there is a consistent failure in some of the paths , you might want to set a minimum or maximum delay constraint for that critical path inside the /hardware/top.sdc file.
For related issues, you can refer to the following workaround method on the Knowledge Database page—How to close timing on competing hold and setup violations in Arria 10?
3. MMD and OpenCL™ Utilities
MMD Source Development or Modification
MMD software library implements basic input/output (I/O) between the host and the acceleration board and provides interfaces, such as open, read, and write. The MMD library driver is stored as Windows* 64 or Linux* 64 formats, and the source code is stored in the source folder.
For more information, refer to the Creating the MMD Library section in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.
Utility Support
OpenCL™ utilities allow you to perform board access using Intel® FPGA SDK for OpenCL™. This includes aocl install, aocl uninstall, aocl diagnose, aocl program, and aocl flash.
For more information, refer to the Providing Intel® FPGA SDK for OpenCL™ Utilities Support section in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.
After you create the software utilities and the MMD layer, the hardware design needs to be tested. The standard way is to generate the boardtest kernel and run on the board.
For more information, refer to the Testing the Hardware Design section in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.
4. Debug
Board Bring-Up
This section helps you to troubleshoot issues while bringing up either Intel® FPGA development kits or your own custom boards.
To find out some known issues that you might face while bringing up your boards, refer to the following sections in AN 807: Configuring the Intel® Arria® 10 GX FPGA Development Kit for the Intel® FPGA SDK for OpenCL™ Application Note:
- Troubleshooting section
- Possible Errors after Running the Diagnose Utility section
Floorplan and Timing
For tips and tricks on using minimal area for the static logic and leaving more space for your OpenCL™ kernel, you can refer to the AN 824: Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide.
Runtime Debug
There are certain environment variables that can be set to get more debug information while running the host application. These are Intel® FPGA SDK for OpenCL™ specific environment variables, which can help diagnose problems with custom platform designs.
The following table lists all of these environment variables as well as describes them in detail.
Environment Variable |
Description |
ACL_HAL_DEBUG |
Set this variable to a value of 1 to 5 to increase debug output from the Hardware Abstraction Layer (HAL), which interfaces directly with the MMD layer. |
ACL_PCIE_DEBUG |
Set this variable to a value of 1 to 10000 to increase debug output from the MMD. This variable setting is useful for confirming that the version ID register was read correctly and the UniPHY IP cores are calibrated. |
ACL_PCIE_JTAG_CABLE |
Set this variable to override the default quartus_pgm argument that specifies the cable number. The default is cable 1. If there are multiple Intel® FPGA Download Cable, you can specify a particular cable by setting this variable. |
ACL_PCIE_JTAG_DEVICE_INDEX |
Set this variable to override the default quartus_pgm argument that specifies the FPGA device index. By default, this variable has a value of 1. If the FPGA is not the first device in the JTAG chain, you can customize the value. |
ACL_PCIE_USE_JTAG_PROGRAMMING |
Set this variable to force the MMD to reprogram the FPGA using the JTAG cable instead of Partial Reconfiguration. |
ACL_PCIE_DMA_USE_MSI |
Set this variable if you want to use MSI for direct memory access (DMA) transfers on Windows*. |
Signal Tap Debug
Because OpenCL™ designs do not support simulation feature, using the Signal Tap Logic Analyzer is the best way to debug these designs.
To debug any design where there is a kernel hang or an issue related to memory interface or aocl diagnose failure, using the Signal Tap Logic Analyzer is recommended.
To learn more about the Signal Tap Logic Analyzer, refer to the Design Debugging with the Signal Tap Logic Analyzer section in the Debug Tools User Guide.
Perform the following steps to add the Signal Tap file into the BSP design
1. Open the Signal Tap GUI and add all the signals to be analyzed.
2. Save the STP file in the same directory as the Intel® Quartus® software project file.
3. Add the following command lines into your flat.qsf:
- set_global_assignment -name ENABLE_SIGNALTAP ON
- set_global_assignment -name USE_SIGNALTAP_FILE <file_name>.stp
- set_global_assignment -name SIGNALTAP_FILE <file_name>.stp
4. Recompile the kernel from the AOCL command line.
Knowledge Database Solution
Intel® Arria® 10 Devices
Intel® Stratix® 10 Devices
Known Issues
Additional Resources
Design Debugging Using In-System Sources and Probes section in the Debug Tools User Guide
AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile
5. Recommended Reading and Training
OpenCL™ Training Courses
- Introduction to Parallel Computing with OpenCL™ on Intel® FPGAs
- Running OpenCL™ on Intel® FPGAs
- Building Custom Platforms for Intel® FPGA SDK for OpenCL™: Board Support Package (BSP) Contents
- Developing a Custom OpenCL™ Board Support Package (BSP)
- OpenCL™ Board Support Package (BSP) Training Courses
- Other OpenCL™ Training Courses
OpenCL™ Videos
Title |
Description |
|---|---|
This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ fast Fourier transform (FFT) on the Cyclone® V SoC using a Windows* machine. |
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This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ FFT on the Cyclone® V SoC using a Windows* machine. |
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This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ FFT on the Cyclone® V SoC using a Windows* machine. |
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This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ FFT on the Cyclone® V SoC using a Windows* machine. |
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This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ FFT on the Cyclone® V SoC using a Windows* machine. |
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How to Package Custom Verilog Modules/Designs as OpenCL™ Libraries |
The video discusses why customers could potentially use this feature to have their custom processing blocks (RTL) in OpenCL™ kernel code. The video explains the design example such as the make files, config files, and explains the compilation flow. The video also show a demo of the design example. |
OpenCL™ on Intel FPGA SoC FPGA (Linux Host) – Part 1 – Tools Download and Setup |
This video shows you how to download, install, and configure the tools required to develop OpenCL™ kernels and host code targeting Intel FPGA SoC FPGAs. |
This video shows you how to download and compile an example OpenCL™ application targeting the emulator that is built into the Intel FPGA OpenCL™. |
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OpenCL™ on Intel FPGA SoC FPGA (Linux Host) – Part 3 – Kernel and Host Code Compilation for SoC FPGA |
This video shows you how to compile the OpenCL™ kernel and host code targeting the FPGA and processor of the Cyclone® V SoC FPGA. |
OpenCL™ on Intel FPGA SoC FPGA (Linux Host) – Part 4 – Setup of the Runtime Environment |
This video shows you how to set up the Cyclone® V SoC board to run the OpenCL™ example, and execute the host code and kernel on the board. |
6. Get Help
OpenCL Certified Service Providers
Intel recommends the following certified service providers that can assist with development of an OpenCL™ board support package for Intel® FPGA boards. These providers have extensive experience in developing high-quality OpenCL board support packages, drivers, and design migration for Intel FPGA boards:
Terasic Inc
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