AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design
Visible to Intel only — GUID: rvt1508846584963
Ixiasoft
Visible to Intel only — GUID: rvt1508846584963
Ixiasoft
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
The Intel® FPGA Triple-Speed Ethernet and on-board PHY chip reference design demonstrates Ethernet operation between the Triple-Speed Ethernet Intel® FPGA IP core and on-board Marvell 88E1111 PHY chip in Intel® Stratix® 10 GX FPGA Development Board. In this reference design, the Triple-Speed Ethernet Intel® FPGA IP is connected to the on-board PHY chip through Serial Gigabit Media Independent Interface (SGMII).
- Features
- Hardware and Software Requirements
- Functional Description
- Hardware Testing
- TCL Script
- Interface Signals
- Configuration Registers and Status Registers
- Regenerating Triple-Speed Ethernet Intel FPGA IP
- Document Revision History for AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel Stratix 10 Devices