Quartus® Prime Design Software Support Center

Quartus® Prime design software topics to guide you through all the software features.

Getting Started

The Quartus® Prime Design Software Suite encompasses all software design tools needed to bring your FPGA from concept to production. The topics on this web page will guide you through all of the Quartus® Prime software features. Select your area of interest and navigate to the specific resources you need in the Quartus® Prime design flow.

Quartus® Prime User Guides

Quartus® Prime Software Training

Altera offers several types of training, both online and in-person to help get you up to speed quickly on the Quartus® Prime design flow. Here are some suggested training classes to get you started.

Quartus® Prime Software Training

Course Name Type Duration
Beginner Workshop for Altera® FPGAs Online Session
 4 Hours 30 minutes
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Many more training courses are available. For a full catalog, go to FPGA Training.

1. I/O Planning

I/O planning is done at an early stage in FPGA design to ensure a successful placement in your target device while meeting dedicated pin and timing constraints.

  • The Quartus® Prime Pro Edition software offers two tools to manage the complex process of meeting the many constraints of I/O placement.
Tool Description I/O Planning Task How to Access
Interface Planner The interface planner tool manages the complexity of integrating multiple modules with hard requirements for pin assignments (for example, PCI Express*, DDR, and phase-locked loop (PLL) intellectual property (IP) cores). The Interface Planner interacts dynamically with the Quartus® Prime Fitter to verify placement legality while you plan. You can evaluate different floorplans using interactive reports to accurately plan the best implementation. Plan interfaces and device periphery Tools > Interface Planner
Pin Planner The pin planner tool is a low-level pin assignment tool. Use this to manually place I/O pins and to specify slew rate and drive strength. Edit, validate, or export pin assignments Assignments > Pin Planner
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I/O Planning Documentation

Software Tool Documentation

Device Documentation

I/O Training

Course Type Duration
Fast & Easy I/O System Design with BluePrint Free, Online 39 minutes
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Other Resources

I/O planning involves many considerations especially when high-speed I/Os or specific protocols are involved.

For more information on I/O management and board development support, visit:

2. Design Entry

Design Entry - Overview

You can express your design using several design entry methods:

  • Using a hardware description language (HDL)
  • Verilog
  • SystemVerilog
  • VHDL
  • Platform Designer, a graphical entry tool for connecting complex modules in a structured way
  • Other high-level entry methods
  • High Level Synthesis (HLS) using C++ to express complex modules
  • OpenCL™ uses C++ to implement computational algorithms across heterogeneous platforms

FPGA Intellectual Property

In addition to direct design entry, FPGAs support a large portfolio of intellectual property (IP) designed specifically for use in FPGAs.

Learning a Hardware Description Language (HDL)

Altera offers several HDL training courses, from free online overviews to full day-long instructor-led classes.

Course Type Duration
Verilog HDL Basics 50 Minutes Online, Free
VHDL Basics 92 Minutes Online, Free
Verilog HDL Advanced 8 Hours Instructor-Led
SystemVerilog with the Quartus® II Software 38 Minutes Online, Free
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Using HDL Templates

The Quartus® Prime software offers several templates for commonly used logic elements such as registers, selected signal assignments, concurrent signal assignments, and subprogram calls. Templates are available in Verilog, SystemVerilog, and VHDL.

If you are unsure of the best way to write a specific function to ensure that it will be implemented correctly, you should refer to these templates. The template system is fully described in the Inserting HDL Code from a Provided Template section in the Design Recommendations User Guide.

Recommended HDL Coding Style

HDL coding styles have a significant effect on the quality of results for logic designs. Synthesis tools will optimize the design, but to achieve precise results, you need to code in a style, which will be readily recognized by the synthesis tool as specific logic constructs.

In addition, there are good design practices, which should be followed for general digital logic design and for LAB-based devices in particular. Managing logic reset methodologies, pipeline delays, and proper synchronous signal generation are some examples of good digital design practices. Some resources for learning good HDL coding practices are listed below.

Resources for Good HDL Coding Style Guidelines

Resource Description
Recommended HDL Coding Styles A section in the Quartus® Prime Pro Edition user guide.
Recommended Design Practices A section in the Quartus® Prime Pro Edition user guide.
Advanced Synthesis Cookbook with design examples PDF with design examples.
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Intellectual Property

Altera FPGAs support a large portfolio of intellectual property (IP) designed specifically for use in FPGAs. Each IP includes a simulation model for design verification before device implementation. See the following links for more information on available IP cores and the IP ecosystem within the Quartus® Prime software.

Resource Description
Altera FPGA IP Portfolio Overview of Altera FPGA IP portfolio.
Introduction to FPGA IP Cores How the IP catalog and parameter editor manage IP cores in the Quartus® Prime software.
FPGA IP Finder A comprehensive list of FPGA IP cores.
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Platform Designer

Platform designer snap

Watch the Introduction to Platform Designer Webcast

The Platform Designer is a graphical, system integration tool that allows you quickly integrate a system of complex components.

Using a standardized interconnection framework (Avalon® or AMBA* AXI*), you can integrate intellectual property from third parties, from your own organization's IP, or from black-box modules yet to be defined. All FPGA IP cores are compliant with Platform Designer interface specifications.

The Platform Designer generates the HDL for instantiation into the rest of your FPGA design.

Platform Designer Documentation

Resource Description
Creating a System with Platform Designer Basics of using the platform designer.
Creating Platform Designer Components How to integrate intellectual property (IP) components for use in the platform designer.
Platform Designer Interconnect Details on the memory-mapped and streaming interfaces available in the Avalon® and AMBA* AXI* interconnection standards.
Optimizing Platform Designer System Performance Optimizing pipelines and dealing with bus arbitration in a platform designer system.
Component Interface Tcl Reference Application programming interface (API) reference for integrating IP into the platform designer system.
Platform Designer System Design Components Description of the interconnection components available in the platform designer.
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Platform Designer (formerly Qsys) Training Courses

Course Duration Type
Creating a System Design with Platform Designer: Getting Started 28 Minutes Free, Online
Introduction to Platform Designer 30 Minutes Free, Online
Introduction to the Platform Designer System Integration Tool 8 Hours Instructor-Led
Platform Designer in the Quartus® Prime Pro Edition Software 63 Minutes Free, Online
Advanced System Design Using Qsys: Component & System Simulation 28 Minutes Free, Online
Advanced System Design Using Platform Designer: System Optimization 46 Minutes Free, Online
Advanced System Design Using Qsys: System Verification with System Console 26 Minutes Free, Online
Advanced System Design Using Qsys: Utilizing Hierarchy 45 Minutes Free, Online
Custom IP Development Using Avalon® and Arm* AMBA* AXI Interfaces 107 Minutes Free, Online
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Platform Designer Design Examples

Resources Description
Platform Designer - Design Example Downloadable design example of a memory tester implemented in the Platform Designer.
AXI* Memory Design Example AMBA* AXI*-3 Agent interface on a simple Verilog custom memory component.
BFM Simulation Example: HPS AXI* Bridge Interface to FPGA Core A hard processor system (HPS) interface to the FPGA AXI* bridge (h2f).
Avalon® Verification IP Suite User Guide (PDF) Bus functional models (BFMs) to verify IP cores using Avalon® interfaces.
Design files (.zip)
Mentor Graphics* AXI* Verification IP Suite (PDF) BFMs to verify IP cores using AMBA* AXI* interfaces.
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White Papers

Resource Description
Comparing IP Integration Approaches for FPGA Implementation Discusses the interconnection challenges in complex FPGA devices.
Applying the Benefits of Network on a Chip Architecture to FPGA System Design Describes the advantages of network on a chip (NoC) architectures in FPGA system design. 
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3. Simulation

Simulation Overview

The Quartus® Prime software supports RTL and gate-level design simulation in supported EDA simulators.

Simulation involves:

  • Setting up your simulator working environment
  • Compiling simulation model libraries
  • Running your simulation

The Quartus® Prime software supports the use of a scripted simulation flow to automate simulation processing in your preferred simulation environment.

In the Quartus® Prime Standard Edition software, you have the option of using the NativeLink tool flow, which automates the launch of your chosen simulator.

Scripted Simulation Flow

Topic Description Pro Edition Standard Edition
Simulating FPGA Designs When using the Platform Designer to configure IP cores and systems, simulation environment setup scripts are generated for supported EDA simulators. Third-party Simulation Third-party Simulation
Aldec Active-HDL This chapter provides specific guidelines for simulation of Quartus® Prime designs with the Aldec Active-HDL or Riviera-PRO software. Aldec Active-HDL and Riviera-PRO Support Aldec Active-HDL and Riviera-PRO Guidelines
Cadence Incisive Enterprise This chapter provides specific guidelines for simulation of Quartus® Prime Pro Edition designs with the Cadence Xcelium* Parallel Simulator software. Cadence Xcelium* Parallel Simulator Support Cadence Simulator Support
Siemens EDA QuestaSim* This chapter provides guidelines for simulation of Quartus® Prime designs with the supported Siemens EDA QuestaSim* simulators. Siemens EDA QuestaSim* Simulator Support Questa* Intel® FPGA Edition, ModelSim® , and Questa* Simulator Support
Synopsys* VCS and VCS MX You can include your supported EDA simulator in the Quartus® Prime design flow. This document provides guidelines for simulation of Quartus® Prime designs with the Synopsys VCS or VCS MX software. Synopsys VCS* and VCS MX Support Synopsys VCS* and VCS MX Support

Refer to the following videos for guidance on setting up simulations:
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NativeLink Simulation Flow

In the Quartus® Prime Standard Edition software, you have the option of using NativeLink. This lets you automatically launch all the steps needed to simulate your design after modifying your source code or IP.

The NativeLink feature integrates your EDA simulator with the Quartus® Prime Standard Edition software by automating the following:

  • Generation of simulator-specific files and simulation scripts.
  • Compilation of simulation libraries.
  • Automatic launching of your simulator following the Quartus® Prime software analysis and elaboration, analysis and synthesis, or after a full compilation.

Resources for NativeLink Simulation Setup

Resources for NativeLink Simulation Setup Resource Type Description
Using NativeLink Simulation User Guide A chapter in the Quartus Prime standard edition user guide: Third-party simulation.
How to set up NativeLink Simulation Video A short video that demonstrates how to set up NativeLink for a simple design.
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Simulation Resources Resource Type Description
Simulating Altera FPGA Designs (Quartus® Prime Pro Edition) User Guide Main documentation for the Quartus® Prime Pro edition software.
Simulating FPGA Designs (Quartus® Prime Standard Edition) Handbook Main documentation for the Quartus® Prime standard edition software.
Generating a Testbench with the Intel® FPGA-ModelSim* Simulation Tool Video This video will provide the easiest way to generate a test bench with Altera-Modelsim. You can modify the test bench with VHDL/ Verilog programming in the test bench generated. Follow FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions.
Simulating a Nios® II Processor Design Video This video describes how to simulate the Nios II processor design. Follow FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions.
How to Simulate Active Serial Memory Interface Block Video This video will show the users how to simulate a simple read and write to a third party flash using active serial memory interface block.
Generating PHYLite Example Design Simulation in ModelSim* in 16.1 with Arria® 10 Video This tutorial video demonstrates how to generate simulation files from custom PHYLite settings in Qsys. It will also guide through how to set up the simulation environment in ModelSim to run PHYLite simulations. This video guide is using Arria 10 specific device, 16.1 Quartus and ModelSim 10.5c.
How to Simulate Cyclone® V 8b10b IP Byte Ordering Video This video will show the users how to perform manual word alignment and byte ordering in the Cyclone V Native PHY with 8b10b and double-width PCS mode. A similar method is applicable to all V series devices. With double-width PCS mode and byte SERDES enabled, the transceiver will achieve a higher data rate.
Simulating Arria® 10 RLDRAM3 Using the Vendor Memory Model Video This video will show the user how to run an example design simulation by to replacing FPGA generic memory model with the vendor memory model.
Simulation of SoC HPS DDR3 Core Video Learn to simulate a DDR3 core from the SoC HPS (Hard Processor System) using Quartus II software v. 13.1 and the Qsys system integration tool, Questa Sim 10.1d and a Linux machine Follow FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions.
Advanced System Design Using Platform Designer: Component & System Simulation
 Online Training

This training is part 1 of 4. The Platform Designer system integration tool saves significant time by automatically generating interconnect logic to connect IP functions and subsystems.

28-minute online course
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4. Synthesis

Synthesis Overview

The Logic Synthesis stage of the Quartus® software design flow will take the register transfer level (RTL) code and create a netlist of lower level primitives (the post-synthesis netlist). The post-synthesis netlist will then be used as an input to the Fitter, which will place and route the design.

The Quartus® Prime and Quartus® II software include advanced integrated synthesis and interfaces with other third-party synthesis tools. The software also offers schematic netlist viewers that you can use to analyze a structure of a design and see how the software interpreted your design.

Synthesis results can be viewed with the Quartus® Netlist viewers, both after RTL elaboration and after Technology Mapping.

Synthesis Documentation

Title Description
Quartus Prime Integrated Synthesis The Quartus® Prime software integrated synthesis tool supports the synthesis of VHDL, Verilog, SystemVerilog, and legacy Altera® FPGA-specific design entry languages.
Synplify Support The Quartus® Prime software tool flow also supports the Synplicity Synplify and Synplify Pro logic synthesizers.
Mentor Graphics* Precision RTL Support The Quartus® Prime software tool flow also supports the Mentor Graphics* Precision RTL Synthesizer.
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Synthesis Training and Demonstrations

Title Description
Using the Quartus® Prime Software: An Introduction (ODSW1100)

Become familiar with the basic Quartus® Prime software design environment. You will learn about a basic FPGA design flow and how to use the Quartus® Prime software in the flow.

This is a 80 minutes online course.
The Quartus® Prime Software Design Series: Foundation (Standard) (ODSW1110)

Learn to use the Quartus® Prime software to develop an FPGA or CPLD design from initial design to device programming.

This is a 3.5-hour online course.
The Quartus® Prime Software Design Series: Foundation (IDSW110)

Create a project, enter design files, compile, and configure your device to see the design working in-system. Enter timing constraints and analyze a design using the Timing Analyzer. Discover how the software interfaces with common EDA tools used for synthesis and simulation.

This is an 8-hour instructor-led course.
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High-Level Synthesis

The High-Level Synthesis (HLS) tool takes in a design description written in C++ and generates RTL code that is optimized for Altera® FPGAs.

For more information on the HLS Compiler, including documentation, examples, and training courses, view the HLS Support Page.

Document Description
HLS Getting Started Guide Shows how to initialize your high-level synthesis compiler environment. Also includes design examples and tutorials to demonstrate ways to effectively use the compiler.
HLS User Guide Provides instructions on synthesizing, verifying, and simulating IP cores for Altera® FPGA products.
HLS Reference Manual Provides information about the high-level synthesis (HLS) component design flow, including command options and other programming elements you can use in your component code.
HLS Best Practices Guide Offers tips and guidance on how to optimize your component design using information provided by the HLS compiler.
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5. Fitter

Fitter - Pro Edition

With the Quartus® Prime Pro Edition software, the Fitter does its work in individually controllable stages; you can optimize each stage individually by running just that stage of the fitter process, iterating to optimize that stage.

Fitter Stage Incremental Optimization
Plan After this stage, you can run post-plan timing analysis to verify timing constraints and validate cross-clock timing windows. View the placement and periphery properties and perform clock planning for Arria® 10 FPGA and Cyclone® 10 FPGA designs.
Early Place After this stage, the Chip Planner can display an initial high-level placement of design elements. Use this information to guide your floorplanning decisions. For Stratix® 10 FPGA designs, you can also do early clock planning after running this stage.
Place After this stage, validate the resource and logic utilization in the Compilation Reports and review the placement of design elements in the Chip Planner.
Route After this stage, perform detailed setup and hold timing closure in the Timing Analyzer and view routing congestions via the Chip Planner.
Retime After this stage, review the Retiming results in the Fitter report and correct any restrictions limiting further retiming optimization.
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By default, the Fitter will run through all its stages. However, you can analyze the results of Fitter stages to evaluate your design before running the next stage, or before running a full compilation. For more information on how to use the Fitter stages to control the quality of results for your design, refer to the Running the fitter section in the compiler user guide: Quartus® Prime Pro edition.

You can specify several settings to direct the effort level of the Fitter for such things as register packing, register duplication and merging, and overall effort level. For more information on Fitter settings, see discussions under the Fitter settings reference section in the compiler user guide: Quartus® Prime Pro edition.

Fitter - Standard Edition

In the Quartus® Prime Standard Edition software, you can specify several settings to direct the effort level of the Fitter such as register packing, register duplication and merging, and overall effort level. For a complete listing of Fitter Settings, see Compiler Settings Help Page

For more information on Fitter settings, see discussions under

6. Timing Analysis

Timing Analysis Overview

The Timing Analyzer determines the timing relationships that must be met for the design to correctly function and checks arrival times against required times to verify timing.

Timing analysis involves many foundational concepts: asynchronous v. synchronous arcs, arrival and required times, setup and hold requirements, etc. These are defined in the Timing Analysis Basic Concepts section of the Quartus® Prime Standard Edition User Guide: Timing Analyzer.

The Timing Analyzer applies your timing constraints and determines timing delays from the results of the Fitter's implementation of your design into the target device.

The Timing Analyzer must operate from an accurate description of your timing requirements, expressed as timing constraints. The Constraining Designs section of the Quartus® Prime Standard Edition User Guide: Timing Analyzer describes how timing constraints can be added to.sdc files, for use by both the Fitter and the Timing Analyzer.

Timing closure is an iterative process of refining timing constraints; adjusting parameters for synthesis and the Fitter, and managing fitter seed variations.

Timing Analyzer

The Quartus Prime Timing Analyzer

The Timing Analyzer in the Quartus® Prime software is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry standard constraint, analysis, and reporting methodology. The Timing Analyzer can be driven from a graphical user interface or from a command-line interface to constrain, analyze, and report results for all the timing paths in your design.

A full user guide on the Timing Analyzer can be found in the Running the Timing Analyzer section of the Quartus® Prime Standard Edition User Guide: Timing Analyzer.

If you are new to Timing Analysis, see the Recommended Flow for First Time Users section of the Quartus® Prime Standard Edition User Guide: Timing Analyzer. This describes the full design flow using basic constraints.

Training Course Description
Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer You will learn key aspects of the Timing Analyzer GUI in the Quartus® Prime Pro software v. 20.3 with emphasis on evaluating timing reports.
Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections You will learn the concept of collections in the Synopsys* Design Constraints (SDC) format using the Timing Analyzer in the Quartus® Prime Pro software v. 20.3.
Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints You will learn how to create clocks, generated clocks, clock uncertainty, and clock groups using the Synopsys* Design Constraints (SDC) format in the Timing Analyzer in the Quartus® Prime Pro software v. 20.3.
Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces You will learn the basics of constraining I/O interfaces using the Synopsys* Design Constraints (SDC) format in the Timing Analyzer in the Quartus® Prime Pro software v. 20.3.
Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions You will learn about and how to apply the timing exceptions false paths, multicycle paths, and min and max delays using the Synopsys* Design Constraints (SDC) format in the Timing Analyzer in the Quartus® Prime Pro software v. 20.3.
Timing Analysis: Lecture You will learn how to constrain & analyze a design for timing using the Timing Analyzer in the Quartus® Prime Pro software v. 22.1.
Timing Analysis: Hands-on Labs his workshop is a follow on to the Altera FPGA Timing Analysis: Lecture class. There will be a brief review of the SDC constraints learned in the previous class before starting the labs.
Altera® FPGA Timing Closure: Lecture This class teaches the techniques used by design specialists to close timing on designs that “push the envelope” of performance.
Altera® FPGA Timing Closure: Hands-On Lab Your time during this workshop will mostly be spent using the Quartus® Prime Software to practice timing closure techniques.
Timing Closure Using TimeQuest Custom Reporting Learn how to use the Quartus® Prime Timing Closure Recommendations reporting in Timing Analyzer to help you find issues that may be causing timing failures.
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Timing Closure

If the Timing Analyzer determines that your timing specifications are not met, then the design must be optimized for timing until the discrepancy is closed and your timing specifications are met.

Timing closure involves several possible techniques. The most effective techniques will vary with each design. The Timing Closure and Optimization chapter in the Design Optimization User Guide: Quartus Prime Pro Edition gives a lot of practical advice about the timing closure process.

There are several additional training courses to help you understand how to evaluate your design for the right timing closure techniques.

Training Course Duration Type Course Number
Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Timing Closure & Tips 22 Minutes Online, Free OIBBC102
Design Evaluation for Timing Closure 42 Minutes Online, Free ODSWTC02
Best HDL Design Practices for Timing Closure 50 Minutes Online, Free OHDL1130
Timing Closure Using TimeQuest Custom Reporting 21 Minutes Online, Free OTIM1100
Altera® FPGA Timing Closure: Lecture 8 Hours Instructor-Led IDSW145
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7. Design Optimization

Design Optimization Overview

The Quartus® Prime and Quartus® II software include a wide range of features to help you optimize your design for area and timing. This section provides the resources to help you with design optimization techniques and tools.

The Quartus® Prime and Quartus® II software offer physical synthesis netlist optimization to optimize designs further than the standard compilation process. Physical synthesis helps improve the performance of your design, regardless of the synthesis tool used.

Optimization Support Documentation

Title Description
Area and Timing Optimization This user guide section explains how to reduce resource usage, reduce compilation times, and improve timing performance when designing for Altera® devices.
Analyzing and Optimizing the Design Floorplan This user guide section describes how to use the Chip Planner to analyze and optimize the floorplan for your designs. This chapter also explains how to use Logic Lock Region to control the placement.
Engineering Change Management with the Chip Planner This user guide section describes how to use the Chip Planner to implement engineering change orders (ECOs) for supported devices.
Netlist Optimizations and Physical Synthesis This user guide section explains how the netlist optimizations and physical synthesis in Quartus® Prime software can modify your design’s netlist and help improve the quality of your results.
Incremental Compilation Resource Center This resource center web page shows how you can use incremental compilation to reduce compilation times and preserve results during optimization.
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Design Optimization Training Courses

Course Duration Type Course Number
Using Quartus® Prime Pro Software: Chip Planner 29 Minutes Online, Free OPROCHIPPLAN
Using Design Space Explorer 22 Minutes Online, Free ODSE
Timing Closure Using Timing Analyzer Custom Reporting 21 Minutes Online, Free OTIM1100
Best Design Practices for Timing Closure 50 minutes Online, Free OHDL1130
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Design Optimization Tools

The Quartus® Prime software provides tools that present your design in visual ways. These tools let you diagnose any problem areas in your design, in terms of logical or physical inefficiencies.

  • You can use the Netlist Viewers to see a schematic representation of your design at several stages in the implementation process: before synthesis, after synthesis, and after place-and-route. This enables you to confirm your design intent at each stage.
  • The Design Partition Planner helps you visualize and revise a design's partitioning scheme by showing timing information, relative connectivity densities, and the physical placement of partitions. You can locate partitions in other viewers, or modify or delete partitions.
  • With the Chip Planner, you can make floorplan assignments, perform power analysis, and visualize critical paths and routing congestion. The Design Partition Planner and the Chip Planner allow you to partition and layout your design at a higher level.
  • Design Space Explorer II (DSE) automates the search for the settings that give the best results in any individual design. DSE explores the design space of your design, applies various optimization techniques, and analyzes the results to help you discover the best settings for your design.

Using these tools can help you optimize the implementation of the device.

Netlist Viewers

The Quartus® Prime software netlist viewers provide powerful ways to view your design at various stages. Cross probing is possible with other design views: you can select an item and highlight it in the Chip Planner and Design File Viewer windows.

  • The RTL Viewer shows the logic and connections inferred by the synthesizer, after elaboration of the hierarchy and major logic blocks. You can use the RTL Viewer to check your design visually before simulation or other verification processes.
  • The Technology Map Viewer (Post-Mapping) can help you locate nodes in your netlist after synthesis but before place-and-route.
  • The Technology Map Viewer (Post-Fitting) shows the netlist after place-and-route. This can differ from the Post-Mapping netlist because the fitter may make optimizations in order to meet constraints during physical optimization.

The RTL Viewer displays the logic inferred by the Synthesis tool after the elaboration of the hierarchy and major functional blocks.

The Technology Map Viewer shows the logic after synthesis (the "post map view") or after placement and routing (the "post fit view").

Netlist and Finite State Machine Viewers

See a demonstration of the Quartus® software Netlist Viewer and Finite State Machine Viewer in the videos below.

Quartus® Prime Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs (part 1)

The Quartus® Prime RTL Viewer and State Machine Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.

Quartus® Prime Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs (part 2)

The Quartus® Prime RTL Viewer and State Machine Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.

Netlist Viewers Resources

Resource Description
Optimizing the Design Netlist A section in the Quartus® Prime standard edition user guide: Design optimization, covering the use of the Netlist Viewers.
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Chip Planner

Design floorplan analysis helps to close timing and ensure optimal performance in highly complex designs. The Chip Planner in the Quartus® Prime software helps you close timing quickly on your designs. You can use the Chip Planner together with Logic Lock Regions to compile your designs hierarchically and assist with floorplanning. Additionally, use partitions to preserve placement and routing results from individual compilation runs.

You can perform design analysis as well as create and optimize the design floorplan with the Chip Planner. To make I/O assignments, use the Pin Planner.

Chip Planner resources.

Resource Type Description
Analyzing and optimizing the design floorplan Design Optimization User Guide: Quartus® Prime Pro Edition Chapter Primary documentation for design floorplan and Chip Planner.
Chip Planner instructional video (Part 1 of 2) E2E Video Chip Planner tutorial: Cross Reference Timing Paths, Fan-in, Fan-out, Routing Delays, and Clock Regions.
Chip Planner instructional video (Part 2 of 2) E2E Video Chip Planner tutorial: Routing Utilization, Design Element Search, and Logic Lock Regions.
Making ECO changes using FPGA Quartus Chip Planner and resource property editor (Part 1 of 3) E2E Video Making late, small engineering change order (ECO) changes using the Chip Planner.
Making ECO changes using FPGA Quartus Chip Planner and resource property editor (Part 2 of 3) E2E Video Making late, small ECO changes using the Chip Planner.
Making ECO changes using FPGA Quartus Chip Planner and resource property editor (Part 3 of 3) E2E Video Making late, small ECO changes using the Chip Planner.
How to trace the local routing of CDR recovered clock from transceiver channel to I/O pin using the timing analyzer and Chip Planner E2E Video An example of how to use the Chip Planner with the timing analyzer.
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Design Space Explorer II

Design Space Explorer II (DSE) allows you to explore the many parameters available for design compilation.

You can use the DSE to manage multiple compilations with different parameters to find the best combination of parameters that allow you to achieve timing closure.

Design Space Explorer II resources.

Resource Description
Optimizing with Design Space Explorer II Getting Started User Guide: Quartus® Prime Pro Edition.
Design Space Explorer (DSE) Design Example An example of a design space exploration.
Using Design Space Explorer (ODSE) Free online training, 21 minutes.
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8. On-Chip Debugging

As FPGAs increase in performance, size, and complexity, the verification process can become a critical part of the FPGA design cycle. To alleviate the complexity of the verification process, Altera provides a portfolio of on-chip debugging tools. The on-chip debugging tools allow real-time capture of internal nodes in your design to help you verify your design quickly without the use of external equipment, such as a bench logic analyzer or protocol analyzer. This can alleviate the number of pins needed for board-level signal probing. For a guide to all the tools in the debug portfolio, refer to the System Debugging Tools section in the Debug Tools User Guide: Quartus® Prime Pro Edition.

Resource Description
System Console Analyzing and Debugging Designs with System Console.

Cyclone® 10 GX Transceiver PHY User Guide

Arria® 10 Transceiver PHY User Guide

 Transceiver Native PHY Toolkit.
Signal Tap Logic Analyzer Design Debugging with the Signal Tap Logic Analyzer.
Signal Probe The Signal Probe incremental routing feature helps reduce the hardware verification process and time-to-market for system-on-a-programmable-chip (SOPC) designs.
Logic Analyzer Interface In-System Debugging Using External Logic Analyzers.
In-System Sources and Probes Drive and sample logic values using JTAG.
In-System Memory Content Editor The Quartus® Prime In-System Memory Content Editor (ISMCE) allows to view and update memories and constants at runtime through the JTAG interface.
Virtual JTAG Interface This Altera FPGA IP allows you to build your own JTAG scan chain by exposing all of the JTAG control signals and configuring your JTAG Instruction Registers (IRs) and JTAG Data Registers (DRs).

External memory debugging is facilitated by the Extermal Memory Interface Toolkit, which is detailed in the External Memory Interface Support Center.

The Transceiver Toolkit offers extensive facilities to verify transceiver signal quality and performance. For more information on this toolkit, see the Transceiver Toolkit product page.
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On-Chip Debug Design Examples

Here are some examples to help you leverage the available features for common debug scenarios.

On-Chip Debugging - Training Courses

Course Duration Type Course Number
SignalTap II Logic Analyzer: Introduction & Getting Started 47 Minutes Online, Free ODSW1164
SignalTap II Logic Analyzer: Basic Trigger Conditions & Configuration 35 Minutes Online, Free ODSW1171
Signal Tap Logic Analyzer: State-Based Triggering, Compilation, & Programming 37 Minutes Online, Free ODSW1172
SignalTap II Logic Analyzer: Data Acquisition & Additional Features 35 Minutes Online, Free ODSW1173
Altera® FPGA Debugging Tools 8 Hours Instructor-Led IDSW135
Debugging JTAG Chain Integrity 26 Minutes Online, Free ODJTAG1110
On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices 30 Minutes Online, Free OMEM1124
System Console 29 Minutes Online, Free OEMB1117
Advanced System Design Using Platform Designer: System Verification with System Console 26 Minutes Online, Free OAQSYSSYSCON
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On-chip Debug - other resources

Resource Description
Virtual JTAG FPGA IP Core User Guide (PDF) The Virtual JTAG FPGA IP core provides access to the PLD source through the JTAG interface.
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems (PDF) Using SignalTap to monitor signals located inside a system module generated by the Platform Designer.
AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer (PDF) This application note examines the use of the Nios® II plug-in within the Signal Tap logic analyzer and presents the capabilities, configuration options, and use-modes for the plug-in.
AN 799: Quick Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile (PDF) This application note showcases a debugging technique that provides easy access to internal device signals without affecting the design.
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Advanced Topics

Block-Based Design Flows

The Quartus® Prime Pro Edition design software offers block-based design flows. There are of two types- the Incremental Block-Based Compilation and Design Block Reuse flows, which allow your geographically diverse development team to collaborate on a design.

Incremental Block-Based Compilation is preserving or emptying a partition within a project. This works with core partitions and requires no additional files or floor planning. The partition can be emptied, preserved at Source, Synthesis, and Final snapshots.

The Design Block Reuse flow enables you to reuse a block of a design in a different project by creating, preserving, and exporting a partition. With this feature, you can expect a clean hand off timing-closed modules between different teams.

Block-Based Design Resources

Rapid Recompile

Rapid Recompile allows the reuse of previous synthesis and fitter results when possible, and does not reprocess unchanged design blocks. Rapid Recompile can reduce total compilation time after making small design changes. Rapid Recompile supports HDL-based functional ECO changes and enables you to reduce your compile time while preserving the performance of unchanged logic.

Rapid Recompile - Support Resources

Resource Description
Running Rapid Recompile Rapid Recompile section in volume 2 of the Quartus® Prime Pro Edition Handbook.
AN 799: Quick Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile (PDF) An application note showing how Rapid Recompile reduces the compile time for small changes.
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Partial Reconfiguration

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function.

You can create multiple personas for a region of your device, and reconfigure that region without impacting operations in areas outside that persona.

For more information on Partial Reconfiguration, see the Partial reconfiguration page.

Scripting

The Quartus® Prime and Quartus® II software includes comprehensive scripting support for command-line and tool command language (Tcl) script design flows. Separate executables for each stage of the software design flow, such as synthesis, fitting, and timing analysis, include options for making common settings and performing common tasks. The Tcl scripting application programming interface (API) includes commands covering basic to advanced functionality.

Command-Line Scripting

You can use Quartus® Prime or Quartus® II software command-line executables in batch files, shell scripts, makefiles, and other scripts. For instance, use the following command to compile an existing project:

$ quartus_sh --flow compile

Tcl Scripting

Use the Tcl API for any of the following tasks:

  • Creating and managing projects
  • Making assignments
  • Compiling designs
  • Extracting report data
  • Performing timing analysis

You can get started with some of the examples in the Quartus® II software Tcl examples web page. Several other resources are listed below.

Scripting Resources

Resource Description
Quartus® II Scripting Reference Manual Covers both Quartus® software command-line executables and Tcl packages and commands from within a Quartus® software shell.
Quartus® Prime Standard Edition Settings File Reference Manual Covers parameter settings found in the Quartus® software Settings File (.qsf).
Command Line Scripting A section of the Quartus Prime Standard Edition User Guide.
Quartus® II Tcl Examples A web page with several useful Tcl script examples.
Command Line Scripting (ODSW1197) Online training presenting the command line scripting capabilities in the Quartus® software (30 min).
Introduction to Tcl (ODSW1180) An Introduction to the Tcl scripting syntax.
Quartus® Prime Software Tcl Scripting This course presents the Tcl scripting capabilities in the Quartus® Prime software. It covers commonly used Quartus Prime software Tcl packages and four common uses of Tcl scripting in the compilation flow, with examples.
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