External Memory Interfaces IP Support Center
The External Memory Interface (EMIF) support page provides design process from start to finish for FPGAs.
Introduction
The External Memory Interface (EMIF) support center provides resources for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices.
You will find information on how to plan, design, implement, and verify your external memory interfaces. You will also find debug, training, and other resource materials on this page.
Get additional support for Agilex™ 7 FPGA Interface Protocol Design, and Agilex™ 5 FPGA Interface Protocol Design. These step-by-step guided journeys for standard development flows surface the key critical resources and documentation.
For other devices, search the Device and Product Support Collections.
1. Device Selection
How to Select a Device
Two tools are available to help you select an FPGA based on your memory requirements:
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EMIF Device Selector |
EMIF Spec Estimator |
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Features |
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Device Support |
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Resources |
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EMIF Tools |
How to select an External Memory Intellectual Property (IP)
To learn about the various memory intellectual property (IP) available, refer to the following online training curriculum:
Training Course |
Supported Devices | Description |
|---|---|---|
| Introduction to Memory Interfaces | Agilex™ 7 F-Series and I-Series
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This training is part 1 of 4. This first part of the training introduces the memory options available and describes how the architecture of these devices makes such performance possible. Additional training in the series are Integration of Memory Interfaces (part 2), and Verifying Memory Interfaces (part 3), and On-Chip Debugging (part 4) |
| Agilex™ 5 | This course covers the different external memory interface options available, as well as the architectural and hard memory controller features for Stratix® 10 and Arria® 10 FPGAs. |
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| DDR5 Memory and the Memory Interface IP | Agilex™ 5 | This training includes a recording of the "DDR5 Memory and the Memory Interface IP Ask an Expert". In this session, FPGA Apps engineers discuss DDR5 memory technology and answer questions about DDR5 and the memory interface IP. |
High Bandwidth Memory (HBM2) Interfaces: Introduction, Architecture |
Stratix® 10 MX | This course covers the benefits of integrating High Bandwidth Memory into the Stratix® 10 MX FPGA devices, features and options for the hardened HBM controller, and how to generate the HBM2 IP. |
| Stratix® 10 MX | This course covers the features and options for the hardened HBM controller, and the Arm* AMBA 4 AXI interface between the controller and user logic. |
2. User Guides and Documentation
How to find Information on the EMIF IP
For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following External Memory Interfaces IP User Guides:
- Please refer to 'User Guides' Section
| Content Type | Agilex™ 7 Device F-Series and I-Series |
Agilex™ 7 Device M-Series |
Agilex™ 5 Device | Agilex™ 3 Device | Stratix® 10 Device | Arria® 10 Device | Cyclone® 10 Device |
|---|---|---|---|---|---|---|---|
| IP User Guide | |||||||
| Design Example User Guide | -
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| FPGA PHY Lite User Guide | - | ||||||
| FPGA HBM2 User Guide | - | - | - | - | - | - | |
| Release Notes | |||||||
| Pin-Out Files |
3. EMIF IP Generation
How to generate the EMIF IP
For detailed information regarding External Memory Interface (EMIF) Intellectual Property (IP) parameters, refer to the following protocol-specific sections within the following EMIF IP User Guides:
Topic |
Agilex™ 7 Device F-Series and I-Series |
Agilex™ 7 Device M-Series |
Agilex™ 5 Device | Stratix® 10 Device |
Arria® 10 Device |
Cyclone® 10 Device |
|---|---|---|---|---|---|---|
EMIF IP Parameter Descriptions |
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Note: For more information on How to Generate the EMIF IP, refer to the below User Guides and Training Courses and Videos sections. |
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How to Perform Functional Simulation
| Topic | Agilex™ 7 Device F-Series and I-Series |
Agilex™ 7 Device M-Series |
Agilex™ 5 Device | Stratix® 10 Device | Stratix® 10 MX Device | Arria® 10 Device | Cyclone® 10 Device |
|---|---|---|---|---|---|---|---|
| Simulating the External Memory Interface User Guides | Simulating Memory IP | ||||||
| Generating a EMIF simulation Design Examples User Guides | Design Example for Simulation | Design Example for Simulation | Design Example for Simulation | Design Example for Simulation | Design Example for Simulation | Design Example for Simulation | Design Example for Simulation |
| Note: For information on how to verify an EMIF design, refer to the 'Training Courses and Video' section for the 'Verifying Memory Interfaces IP' course. | |||||||
Where to find Information on FPGA Resource and Pin Placement
For detailed External Memory Interface (EMIF) pin information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:
Topic |
Agilex™ 7 Device F-Series and I-Series |
Agilex™ 7 Device M-Series |
Agilex™ 5 Device | Stratix® 10 Device |
Arria® 10 Device |
Cyclone® 10 Device |
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EMIF Pin and Resource Planning |
Interface Planner
For information on Interface Planner for resource location assignments, refer to the following online training.
Training Course |
Description |
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This course covers how to implement a design resource floorplan using Interface Planner. Learn about Interface Planner, formerly known as BluePrint, an easy-to-use tool in the Quartus® Prime Pro Edition software that uses the power of the Fitter to create a legal floorplan in minutes. |
Additional Resources for PHY Lite for Parallel Interfaces
| Topic | Supported Device | Description |
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| PHY Lite for Parallel Interfaces FPGA IP User Guide |
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The main use of the PHY Lite for Parallel Interfaces IPs is used for building custom memory interface PHY blocks. Reference this user guide for instructions to interface with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (synchronous mode), and mobile DDR. The PHY Lite for Parallel Interfaces FPGA IP is suitable for simple parallel interfaces. |
4. Board Design and Simulation
Where to Find Information on Board Layout and Design
For detailed External Memory Interface (EMIF) board layout and design information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:
Topic |
Agilex™ 7 Device F-Series and I-Series |
Agilex™ 7 Device M-Series |
Agilex™ 5 Device | Stratix® 10 Device |
Arria® 10 Device |
Cyclone® 10 Device |
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EMIF Board Design Guidelines |
How to Perform Board/Channel Simulation
For information on measuring write-and-read Intersymbol Interference (ISI) and Crosstalk, arranging Command, Address, Control and Data pins, and I/O bank placement restrictions, refer to the following guidelines:
How to Calculate Board Skew and Channel Loss
Two tools are available to help you calculate board skew and channel loss:
Topic |
Board Skew Parameter Tool |
Channel Loss Calculation Tool |
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Features |
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Support |
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Tools |
Where to Find Information on Timing Closure
For information regarding External Memory Interface (EMIF) timing closure, refer to the following section within the EMIF Intellectual Property (IP) User Guides.
Agilex™ 7 Device F-Series and I-Series |
Agilex™ 7 Device M-Series |
Agilex™ 5 Device | Stratix® 10 Device |
Arria® 10 Device |
Cyclone® 10 Device |
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5. Debug
How to Debug External Memory Interface Designs
For information regarding debugging the external memory interface (EMIF) intellectual property (IP), refer to the following section within the EMIF IP User Guides.
| Agilex™ 7 Device | Agilex™ 5 Device | Stratix® 10 Device | Arria® 10 Device | Cyclone® 10 Device |
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How to Use the EMIF Debug Toolkit
Training Course |
Description |
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EMIF Toolkit and On-Chip Debug Toolkit of Memory Interfaces IP in FPGA Devices |
This course covers how to perform debug using the EMIF Toolkit or On-Chip Debug Toolkit, how to use Traffic Generator 2.0, and configure multiple memory interface designs for compatibility with these debug tools. |
Description of features, support and accessibility of the EMIF Debug Toolkit: |
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Features |
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Support |
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Accessibility |
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Mailbox Command Execution Script
Step-by-step instructions:
| Topic | Supported Device | Description |
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| External Memory Interfaces (EMIF) Mailbox Script | Agilex™ 7 M-Series Device Agilex™ 5 Device |
The Mailbox Access Script available to allow you test the command execution. For step-by-step instruction on how to perform Mailbox access, refer to the following user guide: |
Optimizing Controller Performance
For information regarding controller performance and efficiency, refer to the following section within the External Memory Interfaces (EMIF) Intellectual Property (IP) User Guides.
Agilex™ 7 Device F-Series and I-Series |
Agilex™ 7 Device M Series |
Stratix® 10 Device |
Arria® 10 Device |
Cyclone® 10 Device |
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Additional EMIF Debugging Resources
| Topic | Supported Device | Description |
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| Traffic Generator 2.0 User Guide | Agilex™ 7 F-Series and I-Series Devices | The Traffic Generator 2.0 allows you to test and debug your external memory interface through customizable traffic and test patterns. Refer to the following guide and videos for detailed information on how to use the Traffic Generator 2.0 feature. |
| EMIF Example Traffic Generator Video | Arria® 10 Device | Learn how to implement different test patterns on the Arria 10 traffic generator for external memory interface. |
| Debugging Multiple Memory Interfaces User Guide | Arria® 10 Device | For step-by-step instructions on how to daisy-chain multiple memory interfaces for compatibility with the EMIF Debug Toolkit, refer to the following user guide. |
6. Training Courses
Agilex™ 7 Device F-Series and I-Series |
Stratix® 10 Device | Arria® 10 Device |
Cyclone® 10 Device |
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Additional Recommended User Guides
For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following EMIF IP User Guides.
Agilex™ 7 Device F-Series and I-Series |
Agilex™ 7 Device M-Series |
Agilex™ 5 Device | Stratix® 10 Device | Arria® 10 Device |
Cyclone® 10 Device |
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How to Learn About Known Issues Regarding EMIF
For information on current and known issues regarding the EMIF IP, refer to the Knowledge Base:
Additional Documentation
Comprehensive list of FPGA devices and product collections categorized by product lifecycle stages.
Additional Training Courses for External Memory Interfaces
For additional information, search the following resources: Documentation, Training Courses, Videos, Design Examples, and Knowledge Base.
