ID
781679
Date
7/08/2024
Public
Visible to Intel only — GUID: mws1685425577944
Ixiasoft
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
Visible to Intel only — GUID: mws1685425577944
Ixiasoft
1. Quick Start Guide
Updated for: |
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Intel® Quartus® Prime Design Suite 24.1 |
IP Version 22.3.0 |
The F-Tile Triple-Speed Ethernet Intel® FPGA IP for Intel Agilex® 7 provides the capability of generating design examples for selected configurations, which allows you to:
- Compile the design to get an estimate of the IP area usage and timing.
- Simulate the design to verify the IP functionality through simulation.
- Test the design on the hardware using the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Stages for the Design Example