JESD204B/JESD204C IP Core – Support Center

The JESD204B/C FPGA IP core support center provides information on how to select, design, and implement JESD204B/C links. There are also guidelines on how to bring up your system and debug the JESD204B/C links. This page is organized into categories that align with a JESD204B/C system design flow from start to finish.

Get support resources for Agilex™ 7, Agilex™ 5, Stratix® 10, Arria® 10, and Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

Getting Started

1. Device and IP Selection

Which FPGA Family Should I Use?

 *Maximum data rate may reduce with ECC enable. Please refer to Agilex™ 5 FPGAs and SoCs Device Data Sheet for more information.

1. Select Enable Soft PCS to achieve maximum data rate. For the TX IP core, enabling soft PCS incurs an additional 3–8% increase in resource utilization. For the RX IP core, enabling soft PCS incurs an additional 10–20% increase in resource utilization.

2. Refer to the Arria® 10 and Stratix® 10 Device Datasheet for the maximum data rate supported across transceiver speed grades and transceiver power supply operating conditions.

3. When using Soft PCS mode at 15.0 Gbps, the timing margin is very limited. You are advised to enable high fitter effort, register duplication, and register retiming to improve timing performance.

4. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is up to 12.288 Gbps.

5. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 11.0 Gbps.

6. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 10.0 Gbps.

2. Design Flow and IP Integration

Where Can I Find Information on IP integration?

Agilex™ 7 Devices

• AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP
• AN 967: Multiple Device Synchronization in Digital Phased Array System

Stratix® 10 Devices

• AN804: Implementing Synchronized ADC Multi-link Designs with Stratix® 10 JESD204B RX IP Core
• AN804: Implementing Unsynchronized ADC Multi-link Designs with Stratix® 10 JESD204B RX IP Core

Arria® 10 Devices

• AN803: Implementing Synchronized ADC Multi-link Designs with Arria® 10 JESD204B RX IP Core
• AN803: Implementing Unsynchronized ADC Multi-link Designs with Arria® 10 JESD204B RX IP Core
• AN 814: Arria® 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

3. Board Design and Power Management

Pin Connection Guidelines

Agilex™ 7 Devices

• Agilex™ 7 Device Family Pin Connection Guidelines

Agilex™ 5 Devices

• Agilex™ 5 FPGAs and SoCs Pin Connection Guidelines

Stratix® 10 Devices

• Stratix® 10 GX, MX, TX and SX Device Family Pin Connection Guidelines

Arria® 10 Devices

• Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Cyclone® 10 Devices

• Cyclone® 10 GX Device Family Pin Connection Guidelines

Schematic Review

Agilex™ 7 Devices

• Agilex™ 7 Device Schematic Review Worksheet

Agilex™ 5 Devices

• Agilex™ 5 Device Schematic Review Worksheet

Stratix® 10 Devices

• Stratix® 10 Device Schematic Review Worksheet

Cyclone® 10 Devices

• Cyclone® 10 GX Schematic Review Worksheet

Arria® 10 Devices

• Arria® 10 GX, GT, and SX Schematic Review Worksheet

Board Design Guidelines

• Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
• AN 886: Agilex™ 7 Device Design Guidelines
• Agilex™ 5 FPGAs and SoCs Device Design Guidelines
• AN 766: Stratix® 10 Devices, High-Speed Signal Interface Layout Design Guideline
• AN 613: PCB Stackup Design Considerations for FPGAs
• AN 114: Board Design Guidelines for Intel® Programmable Device Packages
• Board Design Guidelines Solutions
• Board Layout Test

Power Management

• Agilex™ 7 Power Management User Guide
• Agilex™ 5 FPGAs and SoCs Power Management User Guide
• AN 910: Agilex™ 7 Power Distribution Network Design Guidelines
• Early Power Estimator (EPE) and Power Analyzer
• AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design
• Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide

Thermal Power Management

Agilex™ 7 Devices

• AN 944: Thermal Modeling for Agilex™ 7 FPGAs with the FPGA Power and Thermal Calculator

Stratix® 10 Devices

• AN 787: Stratix® 10 Thermal Modeling and Management

Power Sequencing

Agilex™ 7, Agilex™ 5, Stratix® 10, Cyclone® 10, and Arria® 10 Devices

• AN 692: Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, Stratix® 10, Agilex™ 5 and Agilex™ 7 Devices

4. Interoperability and Standards Testing

JESD204B FPGA IP Hardware Checkout Reports

Agilex™ 7 Devices

• AN 976: JESD204C FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Agilex™ 7 F-Tile Devices
• AN 876: JESD204C FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Agilex™ F-Tile Devices
• AN 960: JESD204C FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Agilex™ 7 E-Tile Devices

Stratix® 10 Devices

JESD204B

• AN 905: JESD204B FPGA IP and ADI AD9213 Interoperability Report for Stratix® 10 Devices
• AN 915: JESD204B FPGA IP and ADI AD9208 Interoperability Report for Stratix® 10 E-Tile Devices
• AN 890: JESD204B FPGA IP and ADI AD9174 Interoperability Report for Stratix® 10 L-Tile Devices
• AN 823: FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Stratix® 10 Devices
• AN 832: FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Stratix® 10 Devices
• AN 833: Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

JESD204C

• AN 909: JESD204C FPGA IP and TI ADC12DJ5200RF Interoperability Report for Stratix® 10 Devices
• AN 916: JESD204C FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Stratix® 10 E-Tile Devices
• AN 927: JESD204C FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Stratix® 10 E-Tile Devices
• AN 949: JESD204C FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Stratix® 10 E-Tile Devices

Arria® 10 Devices

• AN 710: FPGA JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report
• AN 712: FPGA JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report
• AN 749: FPGA JESD204B IP Core and ADI AD9144 Hardware Checkout Report
• AN 753: FPGA JESD204B IP Core and ADI AD6676 Hardware Checkout Report
• AN 779: FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report
• AN 785: FPGA JESD204B IP Core and ADI AD9162 Hardware Checkout Report
• AN 792: FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
• AN 810: FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

5. Design Examples and Reference Designs

6. Training Courses and Videos

7. Debug

Tools

• FTA JESD204B SYNCN Signal Not De-asserted Issue

User Guides

• JESD204B FPGA IP User Guide - Chapter 6: JESD204B IP Core Debug Guidelines
• AN 871: Quick Guide for Arria® 10 and Cyclone® 10 GX Transceiver High-Speed Link Tuning
• Ethernet Link Inspector User Guide for Stratix® 10 Devices

Intellectual Property (IP) Core Release Notes

• JESD204B FPGA IP Core Release Notes

Additional Resources

Agilex™ 7, Stratix® 10, Arria® 10, and Cyclone® 10 Devices

• E-Tile Transceiver PHY User Guide
• Arria® 10 Transceiver PHY User Guide
• L- and H-Tile Transceiver PHY User Guide
• Cyclone® 10 GX Transceiver PHY User Guide
• F-tile Architecture and PMA and FEC Direct PHY IP User Guide
• PHY Lite for Parallel Interfaces FPGA IP User Guide

Knowledge Base Solution

• Search the Knowledge Base (Agilex™ 7 Devices)
• Search the Knowledge Base (Agilex™ 5 Devices)
• Search the Knowledge Base (Stratix® 10 Devices)
• Search the Knowledge Base (Cyclone® 10 Devices)
• Search the Knowledge Base (Arria® 10 Devices)