AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

Download PDF
ID 683262
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Platform Design Strategy for 56G PAM4 Channels 3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines
2. Platform Design Strategy for 56G PAM4 Channels x
2.1. Intel® Stratix® 10 E-Tile Transceiver Channel Usage Mode 2.2. Intel® Stratix® 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2) 2.3. PCB Design Flow
2.3. PCB Design Flow x
2.3.1. Design Target at 56 Gbps PAM4 Standard 2.3.2. PCB Materials and Stackup Design 2.3.3. FPGA PCB Design 2.3.4. PCB Pre-Layout Simulation Phase 2.3.5. PCB Post-Layout Simulation Phase
2.3.2. PCB Materials and Stackup Design x
2.3.2.1. Insertion Loss 2.3.2.2. Return Loss 2.3.2.3. Package Loss and Crosstalk 2.3.2.4. PCB Via Design 2.3.2.5. PCB Connector 2.3.2.6. Cable Usage in PCB Design
2.3.3. FPGA PCB Design x
2.3.3.1. FPGA PCB Breakout Design and Reference 2.3.3.2. P/N De-skew Strategy on Differential Pairs 2.3.3.3. Crosstalk - NEXT and FEXT in Differential Pairs
1. Introduction
2. Platform Design Strategy for 56G PAM4 Channels
3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

1. Introduction

The Intel® Stratix® 10 E-Tile PCB design guidelines provided in this document are intended to supplement existing Application Notes on PCB design, and not to provide any contradictory information. Intel recommends that you also read the prerequisite Application Notes listed below:
Note that these design guidelines are not tied to any specific platform, which means:
  • These design guidelines do not give specific design parameter values. They only provide examples to illustrate the Signal Integrity (SI) design methodology.
  • You have the freedom to choose the optimized materials, stackups, and other elements based on your application needs.
Signal integrity simulations are recommended for the E-Tile platform channel design. You must understand the key points below to reach your simulation targets and achieve an optimal design:
  • The design margin for E-Tile channels running at 56 Gbps is much smaller than the margin in the 28 Gbps generation due to the additional -9.5 dB intrinsic loss (1/3 NRZ amplitude).
  • Industrial standard organizations like IEEE802.3 already specify the channel checking method Channel Operating Margin (COM) for pass/fail criteria.
  • Intel provides the IBIS-AMI model and its user guide for SI simulations with the E-Tile silicon's electrical behavior in your own application systems.

The application note uses 56 Gbps to describe data rates in general because of the baseline established in the Common Electrical Interface (CEI). However, the actual data rate can be up to 57.8 Gbps.

Level Two Title