Intel® Stratix® 10 Avalon® Streaming (Avalon-ST) IP for PCIe* Design Example User Guide

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ID 683361
Date 3/07/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for the Intel® Stratix® 10 Avalon® -ST Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Design Components 1.2. Hardware and Software Requirements 1.3. Directory Structure 1.4. Generating the Design Example 1.5. Simulating the Design Example 1.6. Compiling the Design Example and Programming the Device 1.7. Installing the Linux Kernel Driver 1.8. Running the Design Example Application
2. Design Example Description x
2.1. Functional Description for PIO Design Example 2.2. Serial Data Signals 2.3. Registers
A. Document Revision History for the Intel® Stratix® 10 Avalon® -ST Hard IP for PCIe* Design Example User Guide x
A.1. Intel® Stratix® 10 Avalon® Streaming (Avalon-ST) IP for PCIe* Design Example User Guide Revision History
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for the Intel® Stratix® 10 Avalon® -ST Hard IP for PCIe* Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 17.1

Using Intel® Quartus® Prime software, you can generate a programmed I/O (PIO) design example for the Intel L-/H-Tile Avalon-ST for PCI Express IP core. The generated design example reflects the parameters that you specify. The PIO example transfers data from a host processor to a target device. It is appropriate for low-bandwidth applications. This design example automatically creates the files necessary to simulate and compile in the Intel® Quartus® Prime software. You can download the compiled design to the Intel® Stratix® 10-GX FPGA Development Board. To download to custom hardware, update the Intel® Quartus® Prime Settings File (.qsf) with the correct pin assignments .

Figure 1. Development Steps for the Design Example
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