Fixed-Point IP Cores (ALTERA_FIXED-POINT_FUNCTIONS) User Guide

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ID 683339
Date 10/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About Fixed-Point IPs 2. Simulating Fixed-Point IP Design Examples 3. Fixed-Point IP Cores Parameters and Signals 4. Document Revision History for the Fixed-Point IPs User Guide
1. About Fixed-Point IPs x
Features 1.1. Fixed-Point IPs Device Family Support
1. About Fixed-Point IPs
2. Simulating Fixed-Point IP Design Examples
3. Fixed-Point IP Cores Parameters and Signals
4. Document Revision History for the Fixed-Point IPs User Guide

1. About Fixed-Point IPs

Updated for:
Intel® Quartus® Prime Design Suite 21.3
IP Version 19.1.1
The fixed-point IPs (ALTERA_FIXED-POINT_FUNCTIONS) allow you to implement simple fixed-point functions in your FPGA design. These IPs are fully parameterizable.
The fixed-point IPs include functions for:
  • Parallel add
  • Modular multiply
  • Divide
  • Square root
  • Simple counter
  • Loadable counter
  • Integer divide

Features

  • Optimized for Intel® HyperFlex™ FPGA architecture
  • Configurable frequency and latency targets for add, multiply, divide, and square root functions.
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