Visible to Intel only — GUID: sam1439888020073
Ixiasoft
1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
3.1. PLLs and Clocking for Stratix® 10 Devices
3.2. Source-Synchronous Timing Budget
3.3. Guideline: LVDS SERDES IP Core Instantiation
3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank
3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1.1. Clocking Differential Transmitters
3.1.2. Clocking Differential Receivers
3.1.3. Guideline: LVDS Reference Clock Source
3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
3.1.6. Guideline: Pin Placement for Differential Channels
3.1.7. LVDS Interface with External PLL Mode
Visible to Intel only — GUID: sam1439888020073
Ixiasoft
1. Stratix® 10 High-Speed LVDS I/O Overview
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
IP Version 20.0.1 |
The Stratix® 10 device family supports high-speed LVDS protocols through the LVDS I/O banks, the LVDS SERDES Intel® FPGA IP, and the GPIO Intel® FPGA IP.
Stratix® 10 devices support LVDS on all LVDS I/O banks:
- All LVDS I/O banks support true LVDS input with RD OCT and true LVDS output buffer.
- The devices do not support emulated LVDS channels.
- The devices support true differential I/O reference clock for the I/O PLL that drives the serializer/deserializer (SERDES).
- You can use each LVDS I/O pins pair as LVDS receiver or LVDS transmitter.
- The LVDS SERDES IP core can place transmitter and receiver channels in the same I/O bank by using the Duplex Feature option.