MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

Download PDF
ID 817561
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Agilex™ 5 FPGA MIPI D-PHY IP 2. Introduction 3. Agilex™ 5 MIPI D-PHY Architecture 4. MIPI D-PHY Interface Design Guidelines 5. Configuring and Generating the MIPI D-PHY IP 6. Interface Signals and Register Maps 7. Document Revision History for Agilex™ 5 FPGA MIPI D-PHY IP User Guide
1. About the Agilex™ 5 FPGA MIPI D-PHY IP x
1.1. Release Information
2. Introduction x
2.1. Supported Data Lanes and Clock Lane Per Single HSIO Bank 2.2. Unsupported Features
3. Agilex™ 5 MIPI D-PHY Architecture x
3.1. Agilex™ 5 MIPI D-PHY TX 3.2. Agilex™ 5 MIPI D-PHY RX 3.3. Initialization and Reset Sequences 3.4. Calibration 3.5. CSR Clock Domain Crossing (CDC)
4. MIPI D-PHY Interface Design Guidelines x
4.1. Identifying Pin Assignments Based on Byte Location 4.2. Assigning the RZQ pin and Dedicated Reference Clock Pin for MIPI D-PHY IP 4.3. Supported I/O Features in MIPI D-PHY I/O Standard 4.4. Using the Remaining I/O Pin from Same Byte Location 4.5. I/O Bank Sharing 4.6. MIPI D-PHY Placement Rules 4.7. MIPI Interface Layout Design Guidelines 4.8. Handling MIPI D-PHY IP Reset
5. Configuring and Generating the MIPI D-PHY IP x
5.1. Creating a MIPI D-PHY Project 5.2. Configuring the D-PHY IP Tab 5.3. Configuring the MIPI D-PHY RX Mode 5.4. Configuring the MIPI D-PHY TX Mode 5.5. Generating the Design Example
5.5. Generating the Design Example x
5.5.1. Generating the Synthesizable MIPI D-PHY Design Example 5.5.2. Generating MIPI D-PHY IP Design Example with External Loopback Enabled for Simulation
5.5.1. Generating the Synthesizable MIPI D-PHY Design Example x
5.5.1.1. Design Example Block Diagram 5.5.1.2. External Interfaces
5.5.2. Generating MIPI D-PHY IP Design Example with External Loopback Enabled for Simulation x
5.5.2.1. Simulation Design Example with External Loopback Enabled Block Diagram 5.5.2.2. Simulating MIPI D-PHY IP Design Example with Modelsim* and Questasim* 5.5.2.3. Simulating MIPI D-PHY IP Design Example with Synopsys VCSMX* and Xcelium*
6. Interface Signals and Register Maps x
6.1. Interface Signals 6.2. Register Maps
6.1. Interface Signals x
6.1.1. General Interface Signals 6.1.2. AXI-Lite Interface 6.1.3. Core Register Bus 6.1.4. D-PHY RX PPI Interface Signals 6.1.5. D-PHY TX PPI Interface Signals 6.1.6. AXI-Lite CSR Access
6.2. Register Maps x
6.2.1. D-PHY IP Registers 6.2.2. D-PHY Traffic Generator (TG) Registers
6.2.1. D-PHY IP Registers x
6.2.1.1. IP_ID 6.2.1.2. IP_CAP 6.2.1.3. D0_CAP 6.2.1.4. DN_CAP 6.2.1.5. RX_CAP 6.2.1.6. TX_CAP 6.2.1.7. TX_PREAMBLE_LEN 6.2.1.8. D-PHY_CSR 6.2.1.9. TX_CLK_LANE_PS 6.2.1.10. RX_DLANE_ERR 6.2.1.11. SKEW_CAL_LEN_B0 6.2.1.12. SKEW_CAL_LEN_B1 6.2.1.13. SKEW_CAL_LEN_B2 6.2.1.14. SKEW_CAL_LEN_B3 6.2.1.15. ALT_CAL_LEN_B0 6.2.1.16. ALT_CAL_LEN_B1 6.2.1.17. ALT_CAL_LEN_B2 6.2.1.18. ALT_CAL_LEN_B3 6.2.1.19. CLK_CSR 6.2.1.20. CLK_STATUS 6.2.1.21. DLANE_CSR_0 6.2.1.22. DLANE_STATUS_0 6.2.1.23. RX_DLANE_DESKEW_DELAY_0 6.2.1.24. RX_DLANE_ERR_0 6.2.1.25. DLANE_CSR_1 6.2.1.26. DLANE_STATUS_1 6.2.1.27. RX_DLANE_DESKEW_DELAY_1 6.2.1.28. RX_DLANE_ERR_1 6.2.1.29. DLANE_CSR_2 6.2.1.30. DLANE_STATUS_2 6.2.1.31. RX_DLANE_DESKEW_DELAY_2 6.2.1.32. RX_DLANE_ERR_2 6.2.1.33. DLANE_CSR_3 6.2.1.34. DLANE_STATUS_3 6.2.1.35. RX_DLANE_DESKEW_DELAY_3 6.2.1.36. RX_DLANE_ERR_3 6.2.1.37. DLANE_CSR_4 6.2.1.38. DLANE_STATUS_4 6.2.1.39. RX_DLANE_DESKEW_DELAY_4 6.2.1.40. RX_DLANE_ERR_4 6.2.1.41. DLANE_CSR_5 6.2.1.42. DLANE_STATUS_5 6.2.1.43. RX_DLANE_DESKEW_DELAY_5 6.2.1.44. RX_DLANE_ERR_5 6.2.1.45. DLANE_CSR_6 6.2.1.46. DLANE_STATUS_6 6.2.1.47. RX_DLANE_DESKEW_DELAY_6 6.2.1.48. RX_DLANE_ERR_6 6.2.1.49. DLANE_CSR_7 6.2.1.50. DLANE_STATUS_7 6.2.1.51. RX_DLANE_DESKEW_DELAY_7 6.2.1.52. RX_DLANE_ERR_7 6.2.1.53. TX_LPX 6.2.1.54. TX_HS_EXIT 6.2.1.55. TX_LP_EXIT 6.2.1.56. TX_CLK_PREPARE 6.2.1.57. TX_CLK_ZERO 6.2.1.58. TX_CLK_POST 6.2.1.59. TX_CLK_PRE 6.2.1.60. TX_HS_PREPARE 6.2.1.61. TX_HS_ZERO 6.2.1.62. TX_HS_TRAIL 6.2.1.63. TX_INIT 6.2.1.64. TX_WAKE 6.2.1.65. RX_CLK_LOSS_DETECT 6.2.1.66. RX_CLK_SETTLE 6.2.1.67. RX_HS_SETTLE 6.2.1.68. RX_INIT 6.2.1.69. RX_CLK_POST 6.2.1.70. RX_CAL_REG_CTRL 6.2.1.71. RX_CAL_STATUS_D-PHY 6.2.1.72. RX_CAL_SKEW_W_START_MUX 6.2.1.73. RX_CAL_SKEW_W_END_MUX 6.2.1.74. RX_CAL_ALT_W_START_MUX 6.2.1.75. RX__CAL_ALT_W_END_MUX 6.2.1.76. RX_DESKEW_DELAY_MUX 6.2.1.77. RX_CAL_STATUS_LANE_MUX 6.2.1.78. PRBS_INIT_0 6.2.1.79. PRBS_INIT_1 6.2.1.80. PRBS_INIT_2 6.2.1.81. PRBS_INIT_3 6.2.1.82. PRBS_INIT_4 6.2.1.83. PRBS_INIT_5 6.2.1.84. PRBS_INIT_6 6.2.1.85. TX_TM_CONTROL 6.2.1.86. TX_MNL_IO_0 6.2.1.87. TX_MNL_D_LP_EN 6.2.1.88. RX_TM_CONTROL
6.2.2. D-PHY Traffic Generator (TG) Registers x
6.2.2.1. TG_TOP_CTRL_0 6.2.2.2. TG_TOP_CTRL_1 6.2.2.3. TG_TOP_DONE 6.2.2.4. TG_TOP_FAIL 6.2.2.5. TG_TOP_TEST_EN 6.2.2.6. TG_TOP_TEST_LINK 6.2.2.7. TARGET_TEST_CNT 6.2.2.8. TCHK_CONTROL 6.2.2.9. TCHK_LINK_STATUS 6.2.2.10. HS_DONE_LANES 6.2.2.11. TCHK_LINK_ERR_STATUS 6.2.2.12. LANE_ERROR_SOT_LANES 6.2.2.13. CAL_ERROR_LANES 6.2.2.14. HS_ERR_LANES 6.2.2.15. HS_TEST_CNT 6.2.2.16. LPDT_TEST_CNT 6.2.2.17. TRIGGER_TEST_CNT 6.2.2.18. ULPS_TEST_CNT 6.2.2.19. TG_RX_OVRD_DATA_PAT 6.2.2.20. TG_RX_BIT_ERROR_CNT 6.2.2.21. TG_RX_HS_TXFER_CNT 6.2.2.22. TG_LINK_CONTROL 6.2.2.23. TG_INIT_CNT 6.2.2.24. TG_HS_LEN 6.2.2.25. TG_LP_LEN 6.2.2.26. TG_SKEW_CAL 6.2.2.27. TG_ALT_CAL 6.2.2.28. TG_PER_SKEW_CAL_LEN 6.2.2.29. TG_TEST_CNT 6.2.2.30. TG_OVRD_DATA_PAT 6.2.2.31. TG_TX_HS_TXFER_CNT
1. About the Agilex™ 5 FPGA MIPI D-PHY IP
2. Introduction
3. Agilex™ 5 MIPI D-PHY Architecture
4. MIPI D-PHY Interface Design Guidelines
5. Configuring and Generating the MIPI D-PHY IP
6. Interface Signals and Register Maps
7. Document Revision History for Agilex™ 5 FPGA MIPI D-PHY IP User Guide

6.2.1. D-PHY IP Registers

The table below provides a register list of a D-PHY link in the IP.

The presence of some registers depends on the link configuration. TX registers exist only when the D-PHY link is configured as TX; RX registers exist only when the link is configured as RX. Any writes to addresses that do not exist are ignored. Reads return 0s.

Table 29.  D-PHY IP Register List
Register Offset Width Access Reset Description
IP_ID 0x00 8 Read Only 0x00 IP Version ID
IP_CAP 0x01 8 Read Only Param Capability Register 0
D0_CAP 0x03 8 Read Only 0x06 Lane 0 Capability
DN_CAP 0x04 8 Read Only 0x02 Lane 1-N Capability
RX_CAP 0x08 8 Read Only Param Rx Capability Register
TX_CAP 0x0C 8 Read Only Param Tx Capability Register
TX_PREAMBLE_LEN 0x0D 8 Read Write Param Tx Preamble Control
D-PHY_CSR 0x10 8 Read Write 0x01 Soft reset / Enable
TX_CLK_LANE_PS 0x11 8 Read Only Param Tx Clock Phase Shift
RX_DLANE_ERR 0x12 8 Read Only 0x00 Data lane 0-7 error status
SKEW_CAL_LEN_B0 0x14 8 Read Only Param Skew calibration length [7:0] - used by TX for inti skew generation when SKEW_CAL_EN=1
SKEW_CAL_LEN_B1 0x15 8 Read Only Param Skew calibration length [15:8] - used by TX for init skew generation when SKEW_CAL_EN=1
SKEW_CAL_LEN_B2 0x16 8 Read Only Param Skew calibration length [23:16] - used by TX for init skew generation when SKEW_CAL_EN=1
SKEW_CAL_LEN_B3 0x17 8 Read Only Param Skew calibration length [31:24] - used by TX for init skew generation when SKEW_CAL_EN=1
ALT_CAL_LEN_B0 0x18 8 Read Only Param Alternate calibration length [7:0] - used by TX for alternate cal generation when ALT_CAL_EN=1
ALT_CAL_LEN_B1 0x19 8 Read Only Param Alternate calibration length [15:8] - used by TX for alternate cal generation when ALT_CAL_EN=1
ALT_CAL_LEN_B2 0x1A 8 Read Only Param Alternate calibration length [23:16] - used by TX for alternate cal generation when ALT_CAL_EN=1
ALT_CAL_LEN_B3 0x1B 8 Read Only Param Alternate calibration length [31:24] - used by TX for alternate cal generation when ALT_CAL_EN=1
CLK_CSR 0x1C 8 Read Write 0x01 Clock lane CSR.
CLK_STATUS 0x1D 8 Read Only 0x00 Clock Status
DLANE_CSR_0 0x20 8 Read Write Param Data Lane 0 CSR 0
DLANE_STATUS_0 0x21 8 Read Only 0x00  
RX_DLANE_DESKEW_DELAY_0 0x22 8 Read Write * Param RX Data lane deskew delay 0
RX_DLANE_ERR_0 0x23 8 Read Write 0x00

Data Lane 0 error status register (RX)
DLANE_CSR_1 0x24 8 Read Write Param Data Lane 1 CSR 0
DLANE_STATUS_1 0x25 8 Read Only 0x00  
RX_DLANE_DESKEW_DELAY_1 0x26 8 Read Write * Param RX Data lane deskew delay 1
RX_DLANE_ERR_1 0x27 8 Read Write 0x00 Data Lane 1 error status register (RX)
DLANE_CSR_2 0x28 8 Read Write Param Data Lane 2 CSR 0
DLANE_STATUS_2 0x29 8 Read Only 0x00  
RX_DLANE_DESKEW_DELAY_2 0x2A 8 Read Write * Param RX Data lane deskew delay 2
RX_DLANE_ERR_2 0x2B 8 Read Write 0x00 Data Lane 2 error status register (RX)
DLANE_CSR_3 0x2C 8 Read Write Param Data Lane 3 CSR 0
DLANE_STATUS_3 0x2D 8 Read Only 0x00  
RX_DLANE_DESKEW_DELAY_3 0x2E 8 Read Write * Param RX Data lane deskew delay 3
RX_DLANE_ERR_3 0x2F 8 Read Write 0x00 Data Lane 3 error status register (RX)
DLANE_CSR_4 0x30 8 Read Write Param Data Lane 4 CSR 0
DLANE_STATUS_4 0x31 8 Read Only 0x00  
RX_DLANE_DESKEWW_DELAY_4 0x32 8 Read Write * Param RX Data lane deskew delay 4
RX_DLANE_ERR_4 0x33 8 Read Write 0x00 Data Lane 4 error status register (RX)
DLANE_CSR_5 0x34 8 Read Write Param Data Lane 5 CSR 0
DLANE_STATUS_5 0x35 8 Read Only 0x00  
RX_DLANE_DESKEW_DELAY_5 0x36 8 Read Write * Param RX Data lane deskew delay 5
RX_DLANE_ERR_5 0x37   Read Write 0x00 Data Lane 5 error status register (RX)
DLANE_CSR_6 0x38 8 Read Write Param Data Lane 6 CSR 0
DLANE_STATUS_6 0x39 8 Read Only 0x00  
RX_DLANE_DESKEW_DELAY_6 0x3A 8 Read Write * Param RX Data lane deskew delay 6
RX_DLANE_ERR_6 0x3B 8 Read Write 0x00 Data Lane 6 error status register (RX)
DLANE_CSR_7 0x3C 8 Read Write Param Data Lane 7 CSR 0
DLANE_STATUS_7 0x3D 8 Read Only 0x00  
RX_DLANE_DESKEW_DELAY_7 0x3E 8 Read Write * Param RX Data lane deskew delay 7
RX_DLANE_ERR_7 0x3F 8 Read Write 0x00 Data Lane 7 error status register (RX)
TX_LPX 0x40 8 Read Write * Param TX_LPX
TX_HS_EXIT 0x41 8 Read Write * Param TX_HS_EXIT
TX_LP_EXIT 0x42 8 Read Write * Param TX_LP_EXIT
TX_CLK_PREPARE 0x44 8 Read Write * Param TX_CLK_PREPARE
TX_CLK_TRAIL 0x45 8 Read Write * Param TX_CLK_TRAIL
TX _CLK_ZERO 0x46 8 Read Write * Param TX _CLK_ZERO
TX_CLK_POST 0x47 8 Read Write * Param TX_CLK_POST
TX _CLK_PRE 0x48 8 Read Write * Param TX _CLK_PRE
TX _HS_PREPARE 0x49 8 Read Write * Param TX _HS_PREPARE
TX _HS_ZERO 0x4A 8 Read Write * Param TX _HS_ZERO
TX_HS_TRAIL 0x4C 8 Read Write * Param TX_HS_TRAIL
TX_INIT 0x4E 8 Read Write * Param TX_INIT
TX_WAKE 0x4F 8 Read Write * Param TX_WAKE
RX_CLK_LOSS_DETECT 0x50 8 Read Write * Param RX_CLK_LOSS_DETECT
RX_CLK_SETTLE 0x51 8 Read Write * Param RX_CLK_SETTLE
RX _HS_SETTLE 0x52 8 Read Write * Param RX _HS_SETTLE
RX_INIT 0x54 8 Read Write * Param RX_INIT
RX_CLK_POST 0x55 8 Read Write * Param RX_CLK_POST
RX_CAL_REG_CRTL 0x60 8 Read Write 0x00 Rx Capability Register
RX_CAL_STATUS_D-PHY 0x61 8 Read Only 0x00 D-PHY Calibration Status Register
RX_CAL_SKEW_W_START_MUX 0x62 8 Read Only 0x00 Window start delay settings for skew calibration for lane CAL_REG_MUXSEL
RX_CAL_SKEW_W_END_MUX 0x63 8 Read Only 0x00 Window end delay settings for skew calibration for lane CAL_REG_MUXSEL
RX_CAL_ALT_W_START_MUX 0x64 8 Read Only 0x00 Window start delta from alternate calibration for lane CAL_REG_MUXSEL
RX_CAL_ALT_W_END_MUX 0x65 8 Read Only 0x00 Window end delta from alternate calibration for lane CAL_REG_MUXSEL
RX_DESKEW_DELAY_MUX 0x66 8 Read Only 0x00 RX deskew delay for lane CAL_REG_MUXSEL
RX_CAL_STATUS_LANE_MUX 0x67 8 Read Only 0x00 Calibration status for lane CAL_REG_MUXSEL
PRBS_INIT_0 0x68 8 Read Write * Param PRBS9 seed value for data lane 0
PRBS_INIT_1 0x69 8 Read Write * Param PRBS9 seed value for data lane 1
PRBS_INIT_2 0x6A 8 Read Write * Param PRBS9 seed value for data lane 2
PRBS_INIT_3 0x6B 8 Read Write * Param PRBS9 seed value for data lane 3
PRBS_INIT_4 0x6C 8 Read Write * Param PRBS9 seed value for data lane 4
PRBS_INIT_5 0x6D 8 Read Write * Param PRBS9 seed value for data lane 5
PRBS_INIT_6 0x6E 8 Read Write * Param PRBS9 seed value for data lane 6
PRBS_INIT_7 0x6F 8 Read Write * Param PRBS9 seed value for data lane 7
TX_TM_CONTROL 0x70 8 Read Write 0x00 TX test mode control register
TX_MNL_IO_0 0x72 8 Read Write 0x00 TX Manual I/O control register 0
TX_MNL_D_LP_EN 0x73 8 Read Write 0x00 TX Manual I/O Data Lane LP (HSb) Control for Data lanes
RX_TM_CONTROL 0x78 8 Read Write 0x00 RX test mode control register


Section Content
IP_ID
IP_CAP
D0_CAP
DN_CAP
RX_CAP
TX_CAP
TX_PREAMBLE_LEN
D-PHY_CSR
TX_CLK_LANE_PS
RX_DLANE_ERR
SKEW_CAL_LEN_B0
SKEW_CAL_LEN_B1
SKEW_CAL_LEN_B2
SKEW_CAL_LEN_B3
ALT_CAL_LEN_B0
ALT_CAL_LEN_B1
ALT_CAL_LEN_B2
ALT_CAL_LEN_B3
CLK_CSR
CLK_STATUS
DLANE_CSR_0
DLANE_STATUS_0
RX_DLANE_DESKEW_DELAY_0
RX_DLANE_ERR_0
DLANE_CSR_1
DLANE_STATUS_1
RX_DLANE_DESKEW_DELAY_1
RX_DLANE_ERR_1
DLANE_CSR_2
DLANE_STATUS_2
RX_DLANE_DESKEW_DELAY_2
RX_DLANE_ERR_2
DLANE_CSR_3
DLANE_STATUS_3
RX_DLANE_DESKEW_DELAY_3
RX_DLANE_ERR_3
DLANE_CSR_4
DLANE_STATUS_4
RX_DLANE_DESKEW_DELAY_4
RX_DLANE_ERR_4
DLANE_CSR_5
DLANE_STATUS_5
RX_DLANE_DESKEW_DELAY_5
RX_DLANE_ERR_5
DLANE_CSR_6
DLANE_STATUS_6
RX_DLANE_DESKEW_DELAY_6
RX_DLANE_ERR_6
DLANE_CSR_7
DLANE_STATUS_7
RX_DLANE_DESKEW_DELAY_7
RX_DLANE_ERR_7
TX_LPX
TX_HS_EXIT
TX_LP_EXIT
TX_CLK_PREPARE
TX_CLK_ZERO
TX_CLK_POST
TX_CLK_PRE
TX_HS_PREPARE
TX_HS_ZERO
TX_HS_TRAIL
TX_INIT
TX_WAKE
RX_CLK_LOSS_DETECT
RX_CLK_SETTLE
RX_HS_SETTLE
RX_INIT
RX_CLK_POST
RX_CAL_REG_CTRL
RX_CAL_STATUS_D-PHY
RX_CAL_SKEW_W_START_MUX
RX_CAL_SKEW_W_END_MUX
RX_CAL_ALT_W_START_MUX
RX__CAL_ALT_W_END_MUX
RX_DESKEW_DELAY_MUX
RX_CAL_STATUS_LANE_MUX
PRBS_INIT_0
PRBS_INIT_1
PRBS_INIT_2
PRBS_INIT_3
PRBS_INIT_4
PRBS_INIT_5
PRBS_INIT_6
TX_TM_CONTROL
TX_MNL_IO_0
TX_MNL_D_LP_EN
RX_TM_CONTROL

Level Two Title