MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 7/08/2024
Public
Document Table of Contents

6.2.1.47. RX_DLANE_DESKEW_DELAY_6

Offset: 0x3A
Default: IP Param
Description: RX Data lane deskew delay 6
Bit Name Access Description
6:0 RX_DLANE_DESKEW_DELAY_6 Read Write *

RX Data lane deskew delay 6.

Manual data Lane 6 deskew delay setting.
Note: * Can be configured as Read Only during IP generation to save resources.