MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 7/08/2024
Public
Document Table of Contents

6.2.1.22. DLANE_STATUS_0

Offset: 0x21
Default: 0x00
Description:  
Bit Name Access Description
0 DLANE_STATUS_0_INIT_DONE Read Only

Data lane init done

For TX with SKEW_CAL_EN (and ALT_CAL_EN) set to 1, this only gets asserted after the calibration is done.