MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 7/08/2024
Public
Document Table of Contents

6.2.1.29. DLANE_CSR_2

Offset: 0x28
Default: IP Param
Description: Data Lane 2 CSR 0
Bit Name Access Description
4 DLANE_CSR_2_RX_MNL_DESKEW_EN Read Write Manual deskew delay enable.
3 DLANE_CSR_2_RX_DESKEW_UPDATE RWSC

A write of '1' to this register will trigger deskew delay update

MNL_DESKEW_EN = 1 - triggers write from RX_DLANE_DESKEW_DELAY_2

MNL_DESKEW_EN = 0 - triggers write from calibration state machine.
0 DLANE_CSR_2_EN Read Write Enable - when enabling, set this register bit first before setting D-PHY_CSR.Enable to 1.