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2.1. FPGA Simulation Essential Elements
2.2. Overview of Simulation Tool Flow
2.3. Simulation Tool Flow
2.4. Supported Hardware Description Languages
2.5. Supported Simulation Types
2.6. Supported Simulators
2.7. Post-Fit Simulation Support by FPGA Family
2.8. Automating Simulation with the Run Simulation Feature
2.9. Intel FPGA Simulation Basics Revision History
2.8.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
2.8.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
2.8.2.3. Launching Simulation with the Run Simulation Feature
2.8.2.4. Running RTL Simulation using Run Simulation
2.8.2.5. Output Directories and Files for Run Simulation
3.1. Types of Questa* Intel® FPGA Edition Commands
3.2. Commands to Invoke Questa* Intel® FPGA Edition
3.3. Commands to Compile, Elaborate, and Simulate
3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation
3.6. Using the Qrun Flow
3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition
3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library
3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work)
3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo
3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1
3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg
3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench
3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy
3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
3.8.1. Post-Synthesis and Post-Fit Netlists for Simulation
3.8.2. Files Required for Gate-Level Simulation
3.8.3. Step 1: Generate Gate-Level Netlists for Simulation
3.8.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation
3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation
3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
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2.8.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
There are both required and optional setting for use of Run Simulation in batch mode.
The following steps describe specifying the required simulation settings for use of Run Simulation in batch mode:
- Set the compatible EDA Simulator executable path. For example:
set_user_option -name EDA_TOOL_PATH_ QUESTA_INTEL /<simulator install path>/questa_fe_tag/24.1/92/linux64/linux_x86_64 set_user_option -name EDA_TOOL_PATH_ QUESTASIM /<simulator install path>/eda/mentor/questasim/2023.4/linux64/linux_x86_64 set_user_option -name EDA_TOOL_PATH_ VCS /<simulator install path>/eda/synopsys/vcsmx/U-2023.03-1/linux64/suse/bin set_user_option -name EDA_TOOL_PATH_ VCS_MX /<simulator install path>/eda/synopsys/vcsmx/U-2023.03-1/linux64/suse/bin set_user_option -name EDA_TOOL_PATH_ACTIVEHDL <drive letter>:\<simulator install path>\eda\aldec\activehdl\13.0\windows64\bin set_user_option -name EDA_TOOL_PATH_RIVIERAPRO /<simulator install path>/eda/aldec/riviera/2023.04.082/linux64/bin set_user_option -name EDA_TOOL_PATH_ XCELIUM /<simulator install path>/eda/cadence/xcelium/23.03.003/linux64/suse/tools.lnx86/bin
- Specify your supported EDA Simulator and HDL:
set_global_assignment -name EDA_SIMULATION_TOOL "<simulator> (HDL)"
If not set, the following is the default setting:
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
Table 15. Settings for EDA Simulator and HDL Simulator Verilog VHDL Questa* Intel® FPGA Edition Questa Intel FPGA (Verilog) Questa Intel FPGA (VHDL) QuestaSim* QuestaSim (Verilog) QuestaSim (VHDL) VCS* VCS N/A VCS* MX VCS MX (Verilog) VCS MX (VHDL) Active-HDL* Active-HDL (Verilog) Active-HDL (VHDL) Riviera-PRO* Riviera-PRO (Verilog) Riviera-PRO (VHDL) Xcelium* Xcelium (Verilog) Xcelium (VHDL) - Set the testbench and simulation file (if any) names, as well as the section ID (arbitrary). This is a multi-value assignment. The following shows an example with the testbench file 1 as the top-level testbench file:
set_global_assignment -name EDA_TEST_BENCH_FILE <testbench file 1> -section_id testbenchSet set_global_assignment -name EDA_TEST_BENCH_FILE <testbench file 2> -section_id testbenchSet set_global_assignment -name EDA_TEST_BENCH_FILE <testbench file 3> -section_id testbenchSet
- Set the top-level module name in the top testbench file.
set_global_assignment -name EDA_TEST_BENCH_TOP_MODULE <testbench top module name> -section_id testbenchSet