Questa* Intel® FPGA Edition Simulation User Guide

ID 730191
Date 4/01/2024
Public
Document Table of Contents

2.8.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)

There are both required and optional setting for use of Run Simulation in batch mode.

The following steps describe specifying the required simulation settings for use of Run Simulation in batch mode:

  1. Set the compatible EDA Simulator executable path. For example:
    set_user_option -name EDA_TOOL_PATH_ QUESTA_INTEL /<simulator install
     path>/questa_fe_tag/24.1/92/linux64/linux_x86_64
    
    set_user_option -name EDA_TOOL_PATH_ QUESTASIM /<simulator install 
     path>/eda/mentor/questasim/2023.4/linux64/linux_x86_64
    
    set_user_option -name EDA_TOOL_PATH_ VCS /<simulator install
     path>/eda/synopsys/vcsmx/U-2023.03-1/linux64/suse/bin
    
    set_user_option -name EDA_TOOL_PATH_ VCS_MX /<simulator install
     path>/eda/synopsys/vcsmx/U-2023.03-1/linux64/suse/bin
    
    set_user_option -name EDA_TOOL_PATH_ACTIVEHDL <drive letter>:\<simulator install 
     path>\eda\aldec\activehdl\13.0\windows64\bin
    
    set_user_option -name EDA_TOOL_PATH_RIVIERAPRO /<simulator install 
    path>/eda/aldec/riviera/2023.04.082/linux64/bin
    
    set_user_option -name EDA_TOOL_PATH_ XCELIUM /<simulator install 
      path>/eda/cadence/xcelium/23.03.003/linux64/suse/tools.lnx86/bin
  2. Specify your supported EDA Simulator and HDL:
    set_global_assignment -name EDA_SIMULATION_TOOL 
    "<simulator> (HDL)"

    If not set, the following is the default setting:

    set_global_assignment -name EDA_SIMULATION_TOOL 
    "Questa Intel FPGA (Verilog)"
    Table 15.  Settings for EDA Simulator and HDL
    Simulator Verilog VHDL
    Questa* Intel® FPGA Edition Questa Intel FPGA (Verilog) Questa Intel FPGA (VHDL)
    QuestaSim* QuestaSim (Verilog) QuestaSim (VHDL)
    VCS* VCS N/A
    VCS* MX VCS MX (Verilog) VCS MX (VHDL)
    Active-HDL* Active-HDL (Verilog) Active-HDL (VHDL)
    Riviera-PRO* Riviera-PRO (Verilog) Riviera-PRO (VHDL)
    Xcelium* Xcelium (Verilog) Xcelium (VHDL)
  3. Set the testbench and simulation file (if any) names, as well as the section ID (arbitrary). This is a multi-value assignment. The following shows an example with the testbench file 1 as the top-level testbench file:
    set_global_assignment -name EDA_TEST_BENCH_FILE <testbench file 1> 
    -section_id testbenchSet
    set_global_assignment -name EDA_TEST_BENCH_FILE <testbench file 2> 
    -section_id testbenchSet
    set_global_assignment -name EDA_TEST_BENCH_FILE <testbench file 3> 
    -section_id testbenchSet
    
  4. Set the top-level module name in the top testbench file.
    set_global_assignment -name EDA_TEST_BENCH_TOP_MODULE <testbench top module name>
     -section_id testbenchSet