Questa* Intel® FPGA Edition Simulation User Guide

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ID 730191
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to the Questa* Intel® FPGA Edition Simulator 2. FPGA Simulation Basics 3. Simulating with Questa* Intel® FPGA Edition 4. Revision History for Questa Intel FPGA Edition Simulation User Guide A. Quartus® Prime Pro Edition User Guides
1. Introduction to the Questa* Intel® FPGA Edition Simulator x
1.1. Simulator Versions and Licensing 1.2. Accessing Siemens EDA-Provided Simulator Documentation 1.3. Document Prerequisites
1.1. Simulator Versions and Licensing x
1.1.1. Comparing Simulator Versions 1.1.2. Post-Fit Simulation Support by FPGA Family
2. FPGA Simulation Basics x
2.1. FPGA Simulation Essential Elements 2.2. Overview of Simulation Tool Flow 2.3. Simulation Tool Flow 2.4. Supported Hardware Description Languages 2.5. Supported Simulation Types 2.6. Supported Simulators 2.7. Post-Fit Simulation Support by FPGA Family 2.8. Automating Simulation with the Run Simulation Feature 2.9. Intel FPGA Simulation Basics Revision History
2.2. Overview of Simulation Tool Flow x
2.2.1. Compilation Stage 2.2.2. Elaboration Stage 2.2.3. Simulation Stage
2.3. Simulation Tool Flow x
2.3.1. Specifying Logical Libraries 2.3.2. Compiling Files Into Library Directories 2.3.3. The Quartus® Prime Simulation Library 2.3.4. Understanding Elaboration 2.3.5. Commands To Configure and Run Simulation 2.3.6. FPGA Simulation Generic Workflow
2.3.1. Specifying Logical Libraries x
2.3.1.1. Why Do We Need Logical Library Names?
2.3.2. Compiling Files Into Library Directories x
2.3.2.1. Inputs to Compilation Commands 2.3.2.2. Order of Files for Compilation Commands 2.3.2.3. Compilation Command Line Options 2.3.2.4. Module Definitions in Library Directories
2.3.3. The Quartus® Prime Simulation Library x
2.3.3.1. The Quartus® Prime Simulation Library Compiler 2.3.3.2. Running the Simulation Library Compiler in a Terminal 2.3.3.3. Running the Simulation Library Compiler in the GUI 2.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
2.3.4. Understanding Elaboration x
2.3.4.1. Elaboration Binding Phase 2.3.4.2. Elaboration Checks 2.3.4.3. Elaboration Options
2.8. Automating Simulation with the Run Simulation Feature x
2.8.1. Setting Up the Run Simulation Feature 2.8.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line)
2.8.1. Setting Up the Run Simulation Feature x
2.8.1.1. Installation Paths for Supported EDA Simulators (EDA Tool Options Page) 2.8.1.2. Simulation Options (Board and IP Settings Page) 2.8.1.3. Simulation Flow Settings (EDA Tool Settings Page) 2.8.1.4. More EDA Netlist Writer Settings (EDA Tool Settings Page)
2.8.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) x
2.8.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode) 2.8.2.2. Optional Simulation Settings for Run Simulation (Batch Mode) 2.8.2.3. Launching Simulation with the Run Simulation Feature 2.8.2.4. Running RTL Simulation using Run Simulation 2.8.2.5. Output Directories and Files for Run Simulation
3. Simulating with Questa* Intel® FPGA Edition x
3.1. Types of Questa* Intel® FPGA Edition Commands 3.2. Commands to Invoke Questa* Intel® FPGA Edition 3.3. Commands to Compile, Elaborate, and Simulate 3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries 3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation 3.6. Using the Qrun Flow 3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition 3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition
3.3. Commands to Compile, Elaborate, and Simulate x
3.3.1. Compilation Command Examples 3.3.2. Finding Logical Library Names in Simulation Library Compiler Output 3.3.3. Elaboration Command Examples 3.3.4. Simulation Command Examples 3.3.5. Complete Tcl Script Example
3.3.1. Compilation Command Examples x
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library 3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work) 3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo 3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1 3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg 3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
3.3.3. Elaboration Command Examples x
3.3.3.1. Elaboration Example 1: Elaborate the Test Top-level Testbench Module 3.3.3.2. Elaboration Example 2: Elaborate the Test Top-level Testbench Module and Preserve All Signals 3.3.3.3. Elaboration Example 3: Elaborate Top-Level Testbench Module my_test
3.3.4. Simulation Command Examples x
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench 3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy 3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation x
3.5.1. Commands Defined in msim_setup.tcl 3.5.2. Example Using msim_setup.tcl without Customization 3.5.3. Example my_sim.tcl Simulation Script 3.5.4. Passing In Custom Compilation and Elaboration Options for msim_setup.tcl 3.5.5. Finding All Custom Variables
3.6. Using the Qrun Flow x
3.6.1. Specifying Simulation File Generation Settings 3.6.2. Generating the Simulation Model and Setup Scripts 3.6.3. Generating the Testbench System 3.6.4. Generating Example Design Simulation Files
3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition x
3.7.1. Simulating an RTL Design without IP Variants or Platform Designer Systems 3.7.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems
3.7.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems x
3.7.2.1. Compilation Stage - Simulation with IP 3.7.2.2. Elaboration Stage - Simulation with IP 3.7.2.3. Simulation Stage - Simulation with IP
3.7.2.1. Compilation Stage - Simulation with IP x
3.7.2.1.1. Customizing the Generated Simulation Script
3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition x
3.8.1. Post-Synthesis and Post-Fit Netlists for Simulation 3.8.2. Files Required for Gate-Level Simulation 3.8.3. Step 1: Generate Gate-Level Netlists for Simulation 3.8.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation 3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation 3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
4. Revision History for Questa Intel FPGA Edition Simulation User Guide x
4.1. Questa Intel FPGA Edition Simulation User Guide Archive
Answers to Top FAQs
1. Introduction to the Questa* Intel® FPGA Edition Simulator
2. FPGA Simulation Basics
3. Simulating with Questa* Intel® FPGA Edition
4. Revision History for Questa Intel FPGA Edition Simulation User Guide
A. Quartus® Prime Pro Edition User Guides

2.8.1.4. More EDA Netlist Writer Settings (EDA Tool Settings Page)

The More EDA Netlist Writer Settings dialog box allows you to specify settings that control how the Compiler generates and formats the gate-level netlist for gate-level simulation. These setting do not apply to RTL simulation.

Click Assignments > Settings > EDA Tool Settings > Simulation > More EDA Netlist Writer Settings to specify any of the following additional options.

Table 14.  More EDA Netlist Writer Settings (EDA Tool Settings Page)
Name Setting Description
Architecture name in VHDL output netlist structure Specify the name of the architecture in the generated VHDL simulation netlist.
Bring out device-wide set/reset signals as ports

Off (Default)

On

 Add the devpor, devclrn, and devoe signals in the design as input ports in the top-level design hierarchy in the Verilog or VHDL simulation netlist for the project.
Do not write top level VHDL entity

Off (Default)

On

 Do not write top-level entity in VHDL Output File (.vho).
Flatten busses into individual nodes

Off (Default)

On

 Flattens all busses when creating the VHDL Output File (.vho). Turn on this option if your third-party EDA environment does not support buses.
Force Gate Level Simulation Registers to initialize to X (don’t care) and propagate X

Off (Default)

On

 Modifies output gate level simulation netlist to force all registers to initialize to X (don’t care) and propagate X.
Generate Power Estimate Scripts

Off (Default)

On

Write scripts for simulation tool to generate .vcd file for outputs for power estimation.

Truncate long hierarchy paths

Off (Default)

On

Truncate hierarchical node names to 80 characters.

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