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Visible to Intel only — GUID: lht1651527964913
Ixiasoft
3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
Once you determine the compilation options and logical library name for each simulation file, you can create the vsim elaboration command. You can then create a Tcl script containing the appropriate commands to compile, elaborate, and simulate the design, as the following example Tcl script for gate-level simulation illustrates.
In this example, the post-fit verilog netlist is top.vo, the testbench file is test.sv, and the top-level testbench module is test. All files compile into the work library.
vlog -sv top.vo test.sv vsim -t ps -L work test add wave -r /* run -all quit
You can save the script as sim.tcl, and run sim.tcl in the Questa Intel FPGA Edition GUI using the vsim -do sim.tcl command.