Questa* Intel® FPGA Edition Simulation User Guide

ID 730191
Date 4/01/2024
Public
Document Table of Contents

2.9. Intel FPGA Simulation Basics Revision History

Document Version Quartus® Prime Version Changes
2024.04.01 24.1
  • Updated simulator versions supported in Supported Simulators topic.
  • Revised Supported Simulation Flows topic to include the Run Simulation feature.
  • Added new Automating Simulation with the Run Simulation Feature section.
  • Applied phase I rebranding throughout.
2023.12.07 23.4
  • Added new Post-Fit Simulation by Intel FPGA Family topic.
  • Updated simulator versions supported in Supported Simulators topic.
2022.12.21 22.4
  • Replaced all content in chapter with newly developed content more suitable for basic understanding of FPGA design simulation.
  • Updated chapter to reflect end of support for ModelSim and relocation of Questa* Intel® FPGA Edition information to new Questa* Intel® FPGA Edition Simulation User Guide.
2022.04.13 22.1
  • Updated simulator versions supported in Simulator Support topic.
  • Added note about longer compilation times to Compiling Simulation Module Libraries topic.
2021.10.05 21.3
  • Updated simulator versions supported in Simulator Support topic.
  • Revised name of Questa* Intel® FPGA Edition and QuestaSim for latest guidelines throughout.
  • Updated default output directory name to questa in Using the EDA Netlist Writer topic.
2021.10.04 21.3
  • Revised Generating IP Simulation Files steps to include generation of all IP in the design at once.
2021.06.21 21.2
  • Changed chapter title to FPGA Simulation Basics from Simulating Intel FPGA Designs.
  • Added support for Questa* Intel® FPGA Edition simulator throughout.
  • Removed support for ModelSim - Intel FPGA Edition simulator throughout.
  • Updated simulator versions supported in Simulator Support topic.
  • Added precompiled libraries footnote to Supported Hardware Description Languages and Compiling Simulation Model Libraries topics.
  • Revised Running a Simulation (Custom Flow) topic to add missing EDA Netlist Writer step and related links.
  • Replaced "Mentor Graphics" with "Siemens EDA" to reflect current company name.
  • Updated Supported Hardware Description Languages for note on schematic conversion.
  • Revised Scripting IP Simulation to correct typo in step 1.
  • Added links to Incorporating Simulator Setup Scripts from the Generated Template topic.
2021.03.29 21.1
  • Added note about X propagation limit of the Quartus® Prime-provided clock divider simulation model to the Compiling Simulation Model Libraries topic.
2020.10.10 20.1
  • Revised Generating IP Simulation Files topic for new simulation file output options.
  • Updated supported simulator versions and removed support for Cadence Incisive Enterprise* in Simulator Support topic.