Questa* Intel® FPGA Edition Simulation User Guide

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ID 730191
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to the Questa* Intel® FPGA Edition Simulator 2. FPGA Simulation Basics 3. Simulating with Questa* Intel® FPGA Edition 4. Revision History for Questa Intel FPGA Edition Simulation User Guide A. Quartus® Prime Pro Edition User Guides
1. Introduction to the Questa* Intel® FPGA Edition Simulator x
1.1. Simulator Versions and Licensing 1.2. Accessing Siemens EDA-Provided Simulator Documentation 1.3. Document Prerequisites
1.1. Simulator Versions and Licensing x
1.1.1. Comparing Simulator Versions 1.1.2. Post-Fit Simulation Support by FPGA Family
2. FPGA Simulation Basics x
2.1. FPGA Simulation Essential Elements 2.2. Overview of Simulation Tool Flow 2.3. Simulation Tool Flow 2.4. Supported Hardware Description Languages 2.5. Supported Simulation Types 2.6. Supported Simulators 2.7. Post-Fit Simulation Support by FPGA Family 2.8. Automating Simulation with the Run Simulation Feature 2.9. Intel FPGA Simulation Basics Revision History
2.2. Overview of Simulation Tool Flow x
2.2.1. Compilation Stage 2.2.2. Elaboration Stage 2.2.3. Simulation Stage
2.3. Simulation Tool Flow x
2.3.1. Specifying Logical Libraries 2.3.2. Compiling Files Into Library Directories 2.3.3. The Quartus® Prime Simulation Library 2.3.4. Understanding Elaboration 2.3.5. Commands To Configure and Run Simulation 2.3.6. FPGA Simulation Generic Workflow
2.3.1. Specifying Logical Libraries x
2.3.1.1. Why Do We Need Logical Library Names?
2.3.2. Compiling Files Into Library Directories x
2.3.2.1. Inputs to Compilation Commands 2.3.2.2. Order of Files for Compilation Commands 2.3.2.3. Compilation Command Line Options 2.3.2.4. Module Definitions in Library Directories
2.3.3. The Quartus® Prime Simulation Library x
2.3.3.1. The Quartus® Prime Simulation Library Compiler 2.3.3.2. Running the Simulation Library Compiler in a Terminal 2.3.3.3. Running the Simulation Library Compiler in the GUI 2.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
2.3.4. Understanding Elaboration x
2.3.4.1. Elaboration Binding Phase 2.3.4.2. Elaboration Checks 2.3.4.3. Elaboration Options
2.8. Automating Simulation with the Run Simulation Feature x
2.8.1. Setting Up the Run Simulation Feature 2.8.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line)
2.8.1. Setting Up the Run Simulation Feature x
2.8.1.1. Installation Paths for Supported EDA Simulators (EDA Tool Options Page) 2.8.1.2. Simulation Options (Board and IP Settings Page) 2.8.1.3. Simulation Flow Settings (EDA Tool Settings Page) 2.8.1.4. More EDA Netlist Writer Settings (EDA Tool Settings Page)
2.8.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) x
2.8.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode) 2.8.2.2. Optional Simulation Settings for Run Simulation (Batch Mode) 2.8.2.3. Launching Simulation with the Run Simulation Feature 2.8.2.4. Running RTL Simulation using Run Simulation 2.8.2.5. Output Directories and Files for Run Simulation
3. Simulating with Questa* Intel® FPGA Edition x
3.1. Types of Questa* Intel® FPGA Edition Commands 3.2. Commands to Invoke Questa* Intel® FPGA Edition 3.3. Commands to Compile, Elaborate, and Simulate 3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries 3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation 3.6. Using the Qrun Flow 3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition 3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition
3.3. Commands to Compile, Elaborate, and Simulate x
3.3.1. Compilation Command Examples 3.3.2. Finding Logical Library Names in Simulation Library Compiler Output 3.3.3. Elaboration Command Examples 3.3.4. Simulation Command Examples 3.3.5. Complete Tcl Script Example
3.3.1. Compilation Command Examples x
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library 3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work) 3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo 3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1 3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg 3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
3.3.3. Elaboration Command Examples x
3.3.3.1. Elaboration Example 1: Elaborate the Test Top-level Testbench Module 3.3.3.2. Elaboration Example 2: Elaborate the Test Top-level Testbench Module and Preserve All Signals 3.3.3.3. Elaboration Example 3: Elaborate Top-Level Testbench Module my_test
3.3.4. Simulation Command Examples x
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench 3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy 3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation x
3.5.1. Commands Defined in msim_setup.tcl 3.5.2. Example Using msim_setup.tcl without Customization 3.5.3. Example my_sim.tcl Simulation Script 3.5.4. Passing In Custom Compilation and Elaboration Options for msim_setup.tcl 3.5.5. Finding All Custom Variables
3.6. Using the Qrun Flow x
3.6.1. Specifying Simulation File Generation Settings 3.6.2. Generating the Simulation Model and Setup Scripts 3.6.3. Generating the Testbench System 3.6.4. Generating Example Design Simulation Files
3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition x
3.7.1. Simulating an RTL Design without IP Variants or Platform Designer Systems 3.7.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems
3.7.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems x
3.7.2.1. Compilation Stage - Simulation with IP 3.7.2.2. Elaboration Stage - Simulation with IP 3.7.2.3. Simulation Stage - Simulation with IP
3.7.2.1. Compilation Stage - Simulation with IP x
3.7.2.1.1. Customizing the Generated Simulation Script
3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition x
3.8.1. Post-Synthesis and Post-Fit Netlists for Simulation 3.8.2. Files Required for Gate-Level Simulation 3.8.3. Step 1: Generate Gate-Level Netlists for Simulation 3.8.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation 3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation 3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
4. Revision History for Questa Intel FPGA Edition Simulation User Guide x
4.1. Questa Intel FPGA Edition Simulation User Guide Archive
Answers to Top FAQs
1. Introduction to the Questa* Intel® FPGA Edition Simulator
2. FPGA Simulation Basics
3. Simulating with Questa* Intel® FPGA Edition
4. Revision History for Questa Intel FPGA Edition Simulation User Guide
A. Quartus® Prime Pro Edition User Guides

2.9. Intel FPGA Simulation Basics Revision History

Document Version Quartus® Prime Version Changes
2024.04.01 24.1
  • Updated simulator versions supported in Supported Simulators topic.
  • Revised Supported Simulation Flows topic to include the Run Simulation feature.
  • Added new Automating Simulation with the Run Simulation Feature section.
  • Applied phase I rebranding throughout.
2023.12.07 23.4
  • Added new Post-Fit Simulation by Intel FPGA Family topic.
  • Updated simulator versions supported in Supported Simulators topic.
2022.12.21 22.4
  • Replaced all content in chapter with newly developed content more suitable for basic understanding of FPGA design simulation.
  • Updated chapter to reflect end of support for ModelSim and relocation of Questa* Intel® FPGA Edition information to new Questa* Intel® FPGA Edition Simulation User Guide.
2022.04.13 22.1
  • Updated simulator versions supported in Simulator Support topic.
  • Added note about longer compilation times to Compiling Simulation Module Libraries topic.
2021.10.05 21.3
  • Updated simulator versions supported in Simulator Support topic.
  • Revised name of Questa* Intel® FPGA Edition and QuestaSim for latest guidelines throughout.
  • Updated default output directory name to questa in Using the EDA Netlist Writer topic.
2021.10.04 21.3
  • Revised Generating IP Simulation Files steps to include generation of all IP in the design at once.
2021.06.21 21.2
  • Changed chapter title to FPGA Simulation Basics from Simulating Intel FPGA Designs.
  • Added support for Questa* Intel® FPGA Edition simulator throughout.
  • Removed support for ModelSim - Intel FPGA Edition simulator throughout.
  • Updated simulator versions supported in Simulator Support topic.
  • Added precompiled libraries footnote to Supported Hardware Description Languages and Compiling Simulation Model Libraries topics.
  • Revised Running a Simulation (Custom Flow) topic to add missing EDA Netlist Writer step and related links.
  • Replaced "Mentor Graphics" with "Siemens EDA" to reflect current company name.
  • Updated Supported Hardware Description Languages for note on schematic conversion.
  • Revised Scripting IP Simulation to correct typo in step 1.
  • Added links to Incorporating Simulator Setup Scripts from the Generated Template topic.
2021.03.29 21.1
  • Added note about X propagation limit of the Quartus® Prime-provided clock divider simulation model to the Compiling Simulation Model Libraries topic.
2020.10.10 20.1
  • Revised Generating IP Simulation Files topic for new simulation file output options.
  • Updated supported simulator versions and removed support for Cadence Incisive Enterprise* in Simulator Support topic.
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