Questa* Intel® FPGA Edition Simulation User Guide

ID 730191
Date 4/01/2024
Public
Document Table of Contents

3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg

After you compile all source files into libraries, the next step is to elaborate the top-level testbench module. Therefore, if you create a single Tcl script for both compilation and elaboration, you place the elaboration command after the compilation commands. The elaboration command accepts as input the top-level testbench module name, and the list of library directories that you create in the compilation step.

vlog -sv my_pkg.sv -work lib_sv
vlog -L lib_sv -sv foo.sv -work lib1

In this example, the second vlog command must specify -L lib_sv to refer to the SystemVerilog package. This is a partial example, as it does not include the commands to create logical libraries lib_sv and lib1, and also excludes the quit command.