Visible to Intel only — GUID: mdv1661817901660
Ixiasoft
Visible to Intel only — GUID: mdv1661817901660
Ixiasoft
2.3.2.2. Order of Files for Compilation Commands
The order of files that you specify to compilation commands is irrelevant for Verilog and SystemVerilog files in many instances. The main exception is when there are files defining SystemVerilog packages, or other files that import or otherwise refer to those SystemVerilog packages.
For example, suppose file multp_pkg.sv defines the SystemVerilog package multp, and the file my_design.sv imports package multp:
- If you compile both multp_pkg.sv and my_design.sv with a single compilation command, you must ensure that multp_pkg.sv occurs before my_design.sv.
- If you compile multp_pkg.sv and my_design.sv using separate compilation commands, you must ensure that you run the command that is compiling multp_pkg.sv first.
VHDL has stricter requirements for ordering the files. For example, when a VHDL file foo.vhd refers to a logical library name lib1, you must compile the files into lib1 first, before compiling foo.vhd into another library.