Questa* Intel® FPGA Edition Simulation User Guide

ID 730191
Date 4/01/2024
Public
Document Table of Contents

3.6.2. Generating the Simulation Model and Setup Scripts

You generate the simulation model and setup scripts for IP components and Platform Designer systems when generating HDL for these IP in your project.

Platform Designer generates the simulation model and setup scripts according to your specifications in Specifying Simulation File Generation Settings.

To generate the simulation model and simulator setup scripts for your Platform Designer system or IP component, follow these steps:
  1. In the Quartus® Prime Pro Edition software, click Tools > Platform Designer and open or create an IP variant or Platform Designer system.
  2. After specifying any IP component or system parameters in the parameter editor, click the Generate HDL button. The Generation dialog box appears.
  3. Under Simulation, select either Verilog or VHDL for Create Simulation Model. Selecting one of these options makes the Modelsim flow selection setting editable.
  4. For Modelsim flow selection, make sure Qrun is selected to enable the Qrun flow. The alternative setting runs the Traditional flow.
    Figure 12. Generation Dialog Box Settings


  5. To specify one or more specific simulators for which to generate simulation files, enable the checkbox for those simulators. To enable generation for all supported simulators, leave all checkboxes disabled (default setting).
  6. Click Generate. Platform Designer generates the simulation models and setup scripts for your system or IP component in the <project>/<IP name>/sim/<vendor> directory.

To generate the simulation model and simulator setup scripts for your Platform Designer system or IP component in batch mode, use this command:

qsys-generate <file> [args] --modelsim_flow=QRUN