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2.1. FPGA Simulation Essential Elements
2.2. Overview of Simulation Tool Flow
2.3. Simulation Tool Flow
2.4. Supported Hardware Description Languages
2.5. Supported Simulation Types
2.6. Supported Simulators
2.7. Post-Fit Simulation Support by FPGA Family
2.8. Automating Simulation with the Run Simulation Feature
2.9. Intel FPGA Simulation Basics Revision History
2.8.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
2.8.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
2.8.2.3. Launching Simulation with the Run Simulation Feature
2.8.2.4. Running RTL Simulation using Run Simulation
2.8.2.5. Output Directories and Files for Run Simulation
3.1. Types of Questa* Intel® FPGA Edition Commands
3.2. Commands to Invoke Questa* Intel® FPGA Edition
3.3. Commands to Compile, Elaborate, and Simulate
3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation
3.6. Using the Qrun Flow
3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition
3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library
3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work)
3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo
3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1
3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg
3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench
3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy
3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
3.8.1. Post-Synthesis and Post-Fit Netlists for Simulation
3.8.2. Files Required for Gate-Level Simulation
3.8.3. Step 1: Generate Gate-Level Netlists for Simulation
3.8.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation
3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation
3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
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3.6.2. Generating the Simulation Model and Setup Scripts
You generate the simulation model and setup scripts for IP components and Platform Designer systems when generating HDL for these IP in your project.
Platform Designer generates the simulation model and setup scripts according to your specifications in Specifying Simulation File Generation Settings.
To generate the simulation model and simulator setup scripts for your Platform Designer system or IP component, follow these steps:
- In the Quartus® Prime Pro Edition software, click Tools > Platform Designer and open or create an IP variant or Platform Designer system.
- After specifying any IP component or system parameters in the parameter editor, click the Generate HDL button. The Generation dialog box appears.
- Under Simulation, select either Verilog or VHDL for Create Simulation Model. Selecting one of these options makes the Modelsim flow selection setting editable.
- For Modelsim flow selection, make sure Qrun is selected to enable the Qrun flow. The alternative setting runs the Traditional flow.
Figure 12. Generation Dialog Box Settings
- To specify one or more specific simulators for which to generate simulation files, enable the checkbox for those simulators. To enable generation for all supported simulators, leave all checkboxes disabled (default setting).
- Click Generate. Platform Designer generates the simulation models and setup scripts for your system or IP component in the <project>/<IP name>/sim/<vendor> directory.
To generate the simulation model and simulator setup scripts for your Platform Designer system or IP component in batch mode, use this command:
qsys-generate <file> [args] --modelsim_flow=QRUN